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x86: ia32: do not use the first megabyte

After witnessing some strange errors with memory not being
what it should be, lifiting everything above 1MB has solved
it. The Zephyr binary was being loaded into memory containing
reserved regions, resulting in data corruption.

We still simulate XIP for testing purposes by setting up the
memory map as follows:

0x000000 - 0x0FFFFF : Non-present
0x100000 - 0x4FFFFF : "Flash" ROM region
0x500000 - 0x8FFFFF : "SRAM" RAM region

For a total of 9 megabytes of physical RAM used.

Fixes problems observed in some large tests when code coverage
is enabled (which increases the amount of RAM used even more).

Fixes: #17782

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
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andrewboie committed Aug 2, 2019
1 parent 02629b6 commit ce3cc4f97469f10536a8ff92ac6f1861c691fcb6
Showing with 6 additions and 7 deletions.
  1. +1 −1 boards/x86/qemu_x86/board.cmake
  2. +1 −1 boards/x86/qemu_x86/qemu_x86.dts
  3. +4 −5 dts/x86/ia32.dtsi
@@ -8,7 +8,7 @@ endif()

set(QEMU_CPU_TYPE_${ARCH} qemu32,+nx,+pae)
set(QEMU_FLAGS_${ARCH}
-m 12
-m 9
-cpu ${QEMU_CPU_TYPE_${ARCH}}
-device isa-debug-exit,iobase=0xf4,iosize=0x04
${REBOOT_FLAG}
@@ -4,7 +4,7 @@

#include <mem.h>

#define DT_FLASH_SIZE DT_SIZE_K(4092)
#define DT_FLASH_SIZE DT_SIZE_K(4096)
#define DT_SRAM_SIZE DT_SIZE_K(4096)

#include <ia32.dtsi>
@@ -28,18 +28,17 @@
};


flash0: flash@1000 {
flash0: flash@100000 {
compatible = "soc-nv-flash";
reg = <0x00001000 DT_FLASH_SIZE>;
reg = <0x00100000 DT_FLASH_SIZE>;
};

sram0: memory@400000 {
sram0: memory@500000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x00400000 DT_SRAM_SIZE>;
reg = <0x00500000 DT_SRAM_SIZE>;
};


soc {
#address-cells = <1>;
#size-cells = <1>;

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