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dts: arm: stm32: add dts support for ADC1 of stm32

All series of stm32 have at least one ADC instance and this commit adds
one ADC node to the root dts file of each soc, and also adds fixing up
mappings to them.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
  • Loading branch information...
cybertale authored and nashif committed May 7, 2019
1 parent 88145db commit da56cad3a45ba203178700cf68330dc9493f1698
@@ -293,6 +293,15 @@
#pwm-cells = <2>;
};
};

adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
interrupts = <12 0>;
status = "disabled";
label = "ADC_1";
};
};
};

@@ -227,6 +227,15 @@
#pwm-cells = <2>;
};
};

adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
};
};
};

@@ -213,6 +213,15 @@
status = "disabled";
label = "OTGFS";
};

adc1: adc@40012000 {
compatible = "st,stm32-adc";
reg = <0x40012000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
};
};

otgfs_phy: otgfs_phy {
@@ -297,6 +297,15 @@
status = "disabled";
label = "RTC_0";
};

adc1: adc@50000000 {
compatible = "st,stm32-adc";
reg = <0x50000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
};
};

usb_fs_phy: usbphy {
@@ -359,6 +359,15 @@
status = "disabled";
label = "RTC_0";
};

adc1: adc@40012000 {
compatible = "st,stm32-adc";
reg = <0x40012000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
};
};

otgfs_phy: otgfs_phy {
@@ -595,6 +595,15 @@
status = "disabled";
label = "RTC_0";
};

adc1: adc@40012000 {
compatible = "st,stm32-adc";
reg = <0x40012000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
};
};

otghs_fs_phy: otghs_fs_phy {
@@ -162,6 +162,15 @@
status = "disabled";
label = "SPI_1";
};

adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
interrupts = <12 0>;
status = "disabled";
label = "ADC_1";
};
};
};

@@ -291,6 +291,15 @@
status = "disabled";
label = "RTC_0";
};

adc1: adc@50040000 {
compatible = "st,stm32-adc";
reg = <0x50040000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
};
};
};

@@ -0,0 +1,41 @@
#
# Copyright (c) 2018, Endre Karlson
# Copyright (c) 2018, Song Qiang <songqiang1304521@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: ST STM32 family ADC
version: 0.1

description: >
This binding gives a base representation of the ST STM32 ADC
inherits:
!include adc.yaml

properties:
compatible:
type: string
category: required
description: compatible strings
constraint: "st,stm32-adc"

reg:
type: array
description: mmio register space
generation: define
category: required

clocks:
type: array
category: required
description: Clock gate control information
generation: define

interrupts:
type: array
category: required
description: required interrupts
generation: define
...
@@ -187,4 +187,11 @@

#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL

#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012400_BASE_ADDRESS
#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012400_IRQ_0
#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012400_IRQ_0_PRIORITY
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012400_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012400_CLOCK_BUS_0

/* End of SoC Level DTS fixup file */
@@ -207,4 +207,11 @@

#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL

#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012400_BASE_ADDRESS
#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012400_IRQ_0
#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012400_IRQ_0_PRIORITY
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012400_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012400_CLOCK_BUS_0

/* End of SoC Level DTS fixup file */
@@ -148,4 +148,11 @@

#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL

#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012000_BASE_ADDRESS
#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012000_IRQ_0
#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012000_IRQ_0_PRIORITY
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012000_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012000_CLOCK_BUS_0

/* End of SoC Level DTS fixup file */
@@ -263,4 +263,12 @@
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
#define DT_RTC_0_CLOCK_BITS DT_ST_STM32_RTC_40002800_CLOCK_BITS
#define DT_RTC_0_CLOCK_BUS DT_ST_STM32_RTC_40002800_CLOCK_BUS

#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_50000000_BASE_ADDRESS
#define DT_ADC_1_IRQ DT_ST_STM32_ADC_50000000_IRQ_0
#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_50000000_IRQ_0_PRIORITY
#define DT_ADC_1_NAME DT_ST_STM32_ADC_50000000_LABEL
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_50000000_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_50000000_CLOCK_BUS_0

/* End of SoC Level DTS fixup file */
@@ -395,4 +395,12 @@
#define DT_RTC_0_CLOCK_BUS DT_ST_STM32_RTC_40002800_CLOCK_BUS

#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL

#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012000_BASE_ADDRESS
#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012000_IRQ_0
#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012000_IRQ_0_PRIORITY
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012000_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012000_CLOCK_BUS_0

/* End of SoC Level DTS fixup file */
@@ -386,4 +386,12 @@
#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS

#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL

#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012000_BASE_ADDRESS
#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012000_IRQ_0
#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012000_IRQ_0_PRIORITY
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012000_LABEL
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012000_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012000_CLOCK_BUS_0

/* End of SoC Level DTS fixup file */
@@ -132,4 +132,12 @@
#define DT_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE

#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL

#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_40012400_BASE_ADDRESS
#define DT_ADC_1_IRQ DT_ST_STM32_ADC_40012400_IRQ_0
#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_40012400_IRQ_0_PRIORITY
#define DT_ADC_1_NAME DT_ST_STM32_ADC_40012400_LABEL
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012400_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012400_CLOCK_BUS_0

/* End of SoC Level DTS fixup file */
@@ -310,4 +310,12 @@
#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS

#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL

#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_50040000_BASE_ADDRESS
#define DT_ADC_1_IRQ DT_ST_STM32_ADC_50040000_IRQ_0
#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_50040000_IRQ_0_PRIORITY
#define DT_ADC_1_NAME DT_ST_STM32_ADC_50040000_LABEL
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_50040000_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_50040000_CLOCK_BUS_0

/* End of SoC Level DTS fixup file */

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