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dts/bindings: Add binding for riscv,cpu-intc

The RISC-V CPU interrupt controller didn't have a binding.  Add a simple
one for it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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galak committed Jun 19, 2019
1 parent 3f9151d commit de3d80828049a013878b24c9459ac428ce18f53b
Showing with 21 additions and 0 deletions.
  1. +21 −0 dts/bindings/interrupt-controller/riscv,cpu-intc.yaml
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#
# Copyright (c) 2019, Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#

title: RISC-V CPU INTC
version: 0.1

description: >
This binding describes the RISC-V CPU Interrupt Controller
inherits:
!include base.yaml

properties:
compatible:
constraint: "riscv,cpu-intc"

"#cells":
- irq

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