From df4fab46c8fdef719442bb7f96189b0c6d923d29 Mon Sep 17 00:00:00 2001
From: "Najumon B.A" <najumon.ba@intel.com>
Date: Fri, 18 Aug 2023 19:24:42 +0530
Subject: [PATCH] boards: x86: add eMMC support for Intel Alder lake platform

add DTS entry for enable eMMC support on Intel Alder lake platform

Signed-off-by: Najumon B.A <najumon.ba@intel.com>
---
 boards/x86/intel_adl/intel_adl_crb.dts |  4 ++++
 dts/x86/intel/alder_lake.dtsi          | 22 ++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/boards/x86/intel_adl/intel_adl_crb.dts b/boards/x86/intel_adl/intel_adl_crb.dts
index 8b67cd5d3652c2a..ba0bd3346ff2c77 100644
--- a/boards/x86/intel_adl/intel_adl_crb.dts
+++ b/boards/x86/intel_adl/intel_adl_crb.dts
@@ -11,6 +11,10 @@
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 	};
+
+	aliases {
+		sdhc0 = &emmc;
+    };
 };
 
 &uart0 {
diff --git a/dts/x86/intel/alder_lake.dtsi b/dts/x86/intel/alder_lake.dtsi
index 71203891f7a26a8..b885c7cefee8e02 100644
--- a/dts/x86/intel/alder_lake.dtsi
+++ b/dts/x86/intel/alder_lake.dtsi
@@ -79,6 +79,28 @@
 			interrupt-parent = <&intc>;
 			status = "disabled";
 		};
+
+		emmc: emmc0 {
+			compatible = "emmc-host";
+			vendor-id = <0x8086>;
+			device-id = <0x54C4>;
+			status = "okay";
+			max-bus-freq = <200000000>;
+			min-bus-freq = <400000>;
+			power-delay-ms = <500>;
+			mmc-hs400-1_8v;
+			mmc-hs200-1_8v;
+			mmc-dw-8bit;
+			mmc-dw-4bit;
+
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			mmc {
+				compatible = "zephyr,mmc-disk";
+				status = "okay";
+			};
+		};
 	};
 
 	soc {