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arch: port nocache linker code to use Cmake function

Remove from linker.ld

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
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oyvindronningstad authored and nashif committed Mar 20, 2019
1 parent 5bebf2a commit e4024e274bd585916b6260bde38e27608cd2561b
Showing with 25 additions and 14 deletions.
  1. +5 −0 arch/common/CMakeLists.txt
  2. +20 −0 arch/common/nocache.ld
  3. +0 −14 include/arch/arm/cortex_m/scripts/linker.ld
@@ -20,3 +20,8 @@ zephyr_linker_sources_ifdef(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT
RAM_SECTIONS
ramfunc.ld
)

zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
RAM_SECTIONS
nocache.ld
)
@@ -0,0 +1,20 @@
/*
* Copyright (c) 2019 Nordic Semiconductor ASA
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/

/* Copied from linker.ld */

/* Non-cached region of RAM */
SECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
{
MPU_ALIGN(_nocache_ram_size);
_nocache_ram_start = .;
*(.nocache)
*(".nocache.*")
MPU_ALIGN(_nocache_ram_size);
_nocache_ram_end = .;
} GROUP_LINK_IN(RAMABLE_REGION)
_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;
@@ -361,20 +361,6 @@ SECTIONS

#endif /* CONFIG_COVERAGE_GCOV */

#if defined(CONFIG_NOCACHE_MEMORY)
/* Non-cached region of RAM */
SECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
{
MPU_ALIGN(_nocache_ram_size);
_nocache_ram_start = .;
*(.nocache)
*(".nocache.*")
MPU_ALIGN(_nocache_ram_size);
_nocache_ram_end = .;
} GROUP_LINK_IN(RAMABLE_REGION)
_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;
#endif /* CONFIG_NOCACHE_MEMORY */

/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/

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