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dts: riscv32: rv32m1: fix reg value for cpu@1

The second cpu core has to have reg = <1>.

See, for example, dts/xtensa/esp32.dtsi.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
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frantony authored and nashif committed May 7, 2019
1 parent 42bdccc commit e44052f25af1d25344bbc0be30b980261ae6cb1e
Showing with 1 addition and 1 deletion.
  1. +1 −1 dts/riscv32/rv32m1.dtsi
@@ -46,7 +46,7 @@
cpu@1 {
device_type = "cpu";
compatible = "riscv";
reg = <0>;
reg = <1>;
};
};

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