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arch: arm: cortex_r: Add memory barriers for register accesses

Cortex R has a write buffer that can cause reordering problems when
accessing memory mapped registers.  Use memory barries to make sure that
these accesses are performed in the desired order.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
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Bradley Bolen authored and ioannisg committed May 29, 2019
1 parent c30a71d commit eb9515ab9c4c9dd3d9dcfdcbed7cf19c245fe60d
Showing with 164 additions and 1 deletion.
  1. +2 −1 include/arch/arm/arch.h
  2. +162 −0 include/arch/arm/cortex_r/sys_io.h
@@ -26,7 +26,6 @@
#include <arch/arm/irq.h>
#include <arch/arm/error.h>
#include <arch/arm/misc.h>
#include <arch/common/sys_io.h>
#include <arch/common/addr_types.h>
#include <arch/common/ffs.h>
#include <arch/arm/nmi.h>
@@ -35,8 +34,10 @@
#ifdef CONFIG_CPU_CORTEX_M
#include <arch/arm/cortex_m/cpu.h>
#include <arch/arm/cortex_m/memory_map.h>
#include <arch/common/sys_io.h>
#elif defined(CONFIG_CPU_CORTEX_R)
#include <arch/arm/cortex_r/cpu.h>
#include <arch/arm/cortex_r/sys_io.h>
#endif

#ifdef __cplusplus
@@ -0,0 +1,162 @@
/*
* Copyright (c) 2015, Wind River Systems, Inc.
* Copyright (c) 2017, Oticon A/S
*
* SPDX-License-Identifier: Apache-2.0
*/

/* "Arch" bit manipulation functions in non-arch-specific C code (uses some
* gcc builtins)
*/

#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_R_SYS_IO_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_R_SYS_IO_H_

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include <zephyr/types.h>
#include <sys/sys_io.h>

/* Memory mapped registers I/O functions */

static ALWAYS_INLINE u8_t sys_read8(mem_addr_t addr)
{
u8_t val = *(volatile u8_t *)addr;

__DMB();
return val;
}

static ALWAYS_INLINE void sys_write8(u8_t data, mem_addr_t addr)
{
__DMB();
*(volatile u8_t *)addr = data;
}

static ALWAYS_INLINE u16_t sys_read16(mem_addr_t addr)
{
u16_t val = *(volatile u16_t *)addr;

__DMB();
return val;
}

static ALWAYS_INLINE void sys_write16(u16_t data, mem_addr_t addr)
{
__DMB();
*(volatile u16_t *)addr = data;
}

static ALWAYS_INLINE u32_t sys_read32(mem_addr_t addr)
{
u32_t val = *(volatile u32_t *)addr;

__DMB();
return val;
}

static ALWAYS_INLINE void sys_write32(u32_t data, mem_addr_t addr)
{
__DMB();
*(volatile u32_t *)addr = data;
}

/* Memory bit manipulation functions */

static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
{
u32_t temp = *(volatile u32_t *)addr;

*(volatile u32_t *)addr = temp | (1 << bit);
}

static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit)
{
u32_t temp = *(volatile u32_t *)addr;

*(volatile u32_t *)addr = temp & ~(1 << bit);
}

static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit)
{
u32_t temp = *(volatile u32_t *)addr;

return temp & (1 << bit);
}

static ALWAYS_INLINE
void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
{
/* Doing memory offsets in terms of 32-bit values to prevent
* alignment issues
*/
sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
}

static ALWAYS_INLINE
void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit)
{
sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
}

static ALWAYS_INLINE
int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
{
return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
}

static ALWAYS_INLINE
int sys_test_and_set_bit(mem_addr_t addr, unsigned int bit)
{
int ret;

ret = sys_test_bit(addr, bit);
sys_set_bit(addr, bit);

return ret;
}

static ALWAYS_INLINE
int sys_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
{
int ret;

ret = sys_test_bit(addr, bit);
sys_clear_bit(addr, bit);

return ret;
}

static ALWAYS_INLINE
int sys_bitfield_test_and_set_bit(mem_addr_t addr, unsigned int bit)
{
int ret;

ret = sys_bitfield_test_bit(addr, bit);
sys_bitfield_set_bit(addr, bit);

return ret;
}

static ALWAYS_INLINE
int sys_bitfield_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
{
int ret;

ret = sys_bitfield_test_bit(addr, bit);
sys_bitfield_clear_bit(addr, bit);

return ret;
}

#endif

#ifdef __cplusplus
}
#endif

#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_R_SYS_IO_H_ */

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