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dts: riscv32: fix reg-names for liteeth

Liteeth exposes two memory regions:
* set of rx/tx buffers (aka slots) to exchange packets,
* control and status registers.

Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
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mateusz-holenko authored and carlescufi committed Jul 23, 2019
1 parent ce4aa11 commit ebd349091a5b15fc8db151f515ae869d4904c525
Showing with 4 additions and 4 deletions.
  1. +3 −3 drivers/ethernet/eth_liteeth.c
  2. +1 −1 dts/riscv32/riscv32-litex-vexriscv.dtsi
@@ -25,21 +25,21 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#define LITEETH_EV_RX 0x1

/* slots */
#define LITEETH_SLOT_BASE DT_INST_0_LITEX_ETH0_BASE_ADDRESS_0
#define LITEETH_SLOT_BASE DT_INST_0_LITEX_ETH0_BUFFERS_BASE_ADDRESS
#define LITEETH_SLOT_RX0 ((LITEETH_SLOT_BASE) + 0x0000)
#define LITEETH_SLOT_RX1 ((LITEETH_SLOT_BASE) + 0x0800)
#define LITEETH_SLOT_TX0 ((LITEETH_SLOT_BASE) + 0x1000)
#define LITEETH_SLOT_TX1 ((LITEETH_SLOT_BASE) + 0x1800)

/* sram - rx */
#define LITEETH_RX_BASE DT_INST_0_LITEX_ETH0_BASE_ADDRESS_1
#define LITEETH_RX_BASE DT_INST_0_LITEX_ETH0_CONTROL_BASE_ADDRESS
#define LITEETH_RX_SLOT ((LITEETH_RX_BASE) + 0x00)
#define LITEETH_RX_LENGTH ((LITEETH_RX_BASE) + 0x04)
#define LITEETH_RX_EV_PENDING ((LITEETH_RX_BASE) + 0x28)
#define LITEETH_RX_EV_ENABLE ((LITEETH_RX_BASE) + 0x2c)

/* sram - tx */
#define LITEETH_TX_BASE ((DT_INST_0_LITEX_ETH0_BASE_ADDRESS_1) + 0x30)
#define LITEETH_TX_BASE ((DT_INST_0_LITEX_ETH0_CONTROL_BASE_ADDRESS) + 0x30)
#define LITEETH_TX_START ((LITEETH_TX_BASE) + 0x00)
#define LITEETH_TX_READY ((LITEETH_TX_BASE) + 0x04)
#define LITEETH_TX_SLOT ((LITEETH_TX_BASE) + 0x0c)
@@ -60,7 +60,7 @@
interrupts = <3 0>;
reg = <0xb0000000 0x2000 0xe0009800 0x6b>;
local-mac-address = [10 e2 d5 00 00 02];
reg-names = "control";
reg-names = "buffers", "control";
label = "eth0";
status = "disabled";
};

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