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x86: add build assert that RAM bounds <= 4GB

DTS will fail this first, but there's no cost to adding
a second level of defense.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
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andrewboie committed Aug 7, 2019
1 parent ce3cc4f commit ec5eb8f7d4da97e9b10d42cd212012b495457fc2
Showing with 6 additions and 0 deletions.
  1. +6 −0 arch/x86/core/ia32/x86_mmu.c
@@ -13,6 +13,12 @@
#include <ctype.h>
#include <string.h>

/* Despite our use of PAE page tables, we do not (and will never) actually
* support PAE. Use a 64-bit x86 target if you have that much RAM.
*/
BUILD_ASSERT(DT_PHYS_RAM_ADDR + (DT_RAM_SIZE * 1024ULL) - 1ULL <=
(unsigned long long)UINTPTR_MAX);

/* Common regions for all x86 processors.
* Peripheral I/O ranges configured at the SOC level
*/

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