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soc/arm: Provide basic support for STM32H7 series

Enable basic support to STM32H7, in single core configuration (M7).

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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erwango authored and nashif committed Jul 1, 2019
1 parent 28d6d75 commit ef35fbcf42bc626e006176243cbc4fbfb8c4eb6a
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# SPDX-License-Identifier: Apache-2.0

zephyr_include_directories(${ZEPHYR_BASE}/drivers)

zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c)
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# Kconfig.defconfig.series - ST Microelectronics STM32H7 MCU line
#
# Copyright (c) 2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#

# Kconfig symbols common to STM32H7 series

if SOC_SERIES_STM32H7X

source "soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7*"

config SOC_SERIES
default "stm32h7"

if GPIO_STM32

# GPIO ports A, B and C are set in ../common/Kconfig.defconfig.series

# empty for now

endif # GPIO_STM32

endif # SOC_SERIES_STM32H7X
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# Kconfig - ST STM32H747X MCU configuration options
#
# Copyright (c) 2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#

if SOC_STM32H747XX

config SOC
string
default "stm32h747xx"

config NUM_IRQS
int
default 150

endif # SOC_STM32H747XX
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# Kconfig - ST Microelectronics STM32H7 MCU series
#
# Copyright (c) 2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#

config SOC_SERIES_STM32H7X
bool "STM32H7x Series MCU"
select CPU_HAS_FPU
select SOC_FAMILY_STM32
select HAS_STM32CUBE
select CPU_HAS_ARM_MPU
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
select NEWLIB_LIBC
help
Enable support for STM32H7 MCU series
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# Kconfig.soc - ST Microelectronics STM32H7 MCU line
#
# Copyright (c) 2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#

choice
prompt "STM32H7x MCU Selection"
depends on SOC_SERIES_STM32H7X

config SOC_STM32H747XX
bool "STM32H747XX"
select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7

endchoice
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/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/

/* SoC level DTS fixup file */

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS

/* End of SoC Level DTS fixup file */
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/* linker.ld - Linker command/script file */

/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <arch/arm/cortex_m/scripts/linker.ld>
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/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/

#ifndef _STM32F7_SOC_H_
#define _STM32F7_SOC_H_

#ifndef _ASMLANGUAGE

#include <stm32h7xx.h>

/* ARM CMSIS definitions must be included before kernel_includes.h.
* Therefore, it is essential to include kernel_includes.h after including
* core SOC-specific headers.
*/
#include <kernel_includes.h>

#endif /* !_ASMLANGUAGE */

#endif /* _STM32F7_SOC_H7_ */
@@ -0,0 +1,57 @@
/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/

/**
* @file
* @brief System/hardware module for STM32H7 CM7 processor
*/

#include <kernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <arch/cpu.h>
#include <cortex_m/exc.h>


/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int stm32h7_init(struct device *arg)
{
u32_t key;

ARG_UNUSED(arg);

key = irq_lock();

SCB_EnableICache();

if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
SCB_EnableDCache();
}

/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();

irq_unlock(key);

/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 64 MHz from HSI */
SystemCoreClock = 64000000;

return 0;
}

SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);

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