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arch: xtensa: Get CPU clock frequency from DTS

The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
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pizi-nordic authored and carlescufi committed Apr 11, 2019
1 parent 1161fdf commit f2d84f08ff7d8905c5b8f2d79d29bb7f0123e0af
@@ -46,10 +46,8 @@
#define XT_BOARD 1
#endif

#ifdef CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
#undef XT_CLOCK_FREQ
#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
#endif
#undef XT_CLOCK_FREQ
#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY

#ifndef XT_TIMER_INDEX
#if defined configXT_TIMER_INDEX
@@ -115,7 +115,7 @@
* anyway!).
*/
#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
#define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
#endif

#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
@@ -0,0 +1,11 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/

/* SoC level DTS fixup file */

#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY

/* End of SoC Level DTS fixup file */
@@ -2,6 +2,8 @@

/* SoC level DTS fixup file */

#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY

#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL
@@ -0,0 +1,11 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/

/* SoC level DTS fixup file */

#define DT_CPU_CLOCK_FREQUENCY DT_SAMPLE_CONTROLLER_0_CLOCK_FREQUENCY

/* End of SoC Level DTS fixup file */

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