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ARC: Add support for ARC HS family of CPU cores

The ARC HS is a family of high performance CPUs from Synopsys
capable of running wide range of applications from heavy DPS
calculation to full-scale OS.

Still as with other ARC cores ARC HS might be tailored to
a particular application.

As opposed to EM cores ARC HS cores always have support of unaligned
data access and by default GCC generates such a data layout with
so we have to always enable unaligned data access in runtime otherwise
on attempt to access such data we'd see "Unaligned memory exception".

Note we had to explicitly mention CONFIG_CPU_ARCEM=y in
all current defconfigs as CPU_ARC{EM|HS} are now parts of a
choice so we cannot simply select ether option in board's Kconfig.

And while at it change "-mmpy-option" of ARC EM to "wlh1"
which is the same as previously used "6" but matches
Programmer's Reference Manual (PRM) and is more human-friendly.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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vonhust authored and andrewboie committed Jun 4, 2019
1 parent 7da47e6 commit f2fd40e90dc548f19a67c38cdc7292388a5ee6f8
@@ -12,17 +12,25 @@ menu "ARC Options"
config ARCH
default "arc"

menu "ARC processor options"
choice
prompt "ARC core family"
default CPU_ARCEM

config CPU_ARCEM
bool
default y
bool "ARC EM cores"
select CPU_ARCV2
select ATOMIC_OPERATIONS_C
help
This option signifies the use of an ARC EM CPU

endmenu
config CPU_ARCHS
bool "ARC HS cores"
select CPU_ARCV2
select ATOMIC_OPERATIONS_BUILTIN
help
This option signifies the use of an ARC HS CPU

endchoice

menu "ARCv2 Family Options"

@@ -119,7 +127,8 @@ config ARC_STACK_PROTECTION
config ARC_USE_UNALIGNED_MEM_ACCESS
bool "Enable unaligned access in HW"
default n if CPU_ARCEM
depends on (CPU_ARCEM && !ARC_HAS_SECURE)
default y if CPU_ARCHS
depends on (CPU_ARCEM && !ARC_HAS_SECURE) || CPU_ARCHS
help
ARC EM cores w/o secure shield 2+2 mode support might be configured
to support unaligned memory access which is then disabled by default.
@@ -5,9 +5,6 @@ if BOARD_EM_STARTERKIT
config BOARD
default "em_starterkit"

config CPU_ARCEM
default y

if GPIO

config GPIO_DW
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_ARC=y
CONFIG_CPU_ARCEM=y
CONFIG_SOC_EMSK=y
CONFIG_SOC_EMSK_EM9D=y
CONFIG_BOARD_EM_STARTERKIT=y
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_ARC=y
CONFIG_CPU_ARCEM=y
CONFIG_SOC_EMSK=y
CONFIG_SOC_EMSK_EM11D=y
CONFIG_BOARD_EM_STARTERKIT=y
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_ARC=y
CONFIG_CPU_ARCEM=y
CONFIG_SOC_EMSK=y
CONFIG_SOC_EMSK_EM7D=y
CONFIG_BOARD_EM_STARTERKIT=y
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_ARC=y
CONFIG_CPU_ARCEM=y
CONFIG_SOC_EMSK=y
CONFIG_SOC_EMSK_EM7D=y
CONFIG_BOARD_EM_STARTERKIT=y
@@ -5,7 +5,4 @@ if BOARD_IOTDK
config BOARD
default "iotdk"

config CPU_ARCEM
default y

endif # BOARD_IOTDK
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: Apache-2.0

CONFIG_ARC=y
CONFIG_CPU_ARCEM=y
CONFIG_SOC_ARC_IOT=y
CONFIG_BOARD_IOTDK=y
CONFIG_XIP=n
@@ -32,5 +32,7 @@ elseif("${ARCH}" STREQUAL "arc")
set(GCC_M_CPU em4_dmips)
elseif(CONFIG_CPU_EM4_FPUDA)
set(GCC_M_CPU em4_fpuda)
elseif(CONFIG_CPU_ARCHS)
set(GCC_M_CPU hs)
endif()
endif()
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata -mmpy-option=6)
zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata)
zephyr_compile_options_ifdef(CONFIG_CPU_ARCEM -mmpy-option=wlh1)
zephyr_compile_options_ifdef(CONFIG_CPU_ARCHS -mmpy-option=plus_qmacw)
zephyr_compile_options_ifdef(CONFIG_FLOAT -mfpu=fpuda_all)

zephyr_sources(

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