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arch/x86: remove support for CONFIG_REALMODE

We no longer support any platforms that bootstrap from real mode.

Fixes: #17166

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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Charles E. Youse authored and andrewboie committed Jul 29, 2019
1 parent e806bd9 commit f7a0dce6365fc77536ac9f8728a4760981e25c2d
Showing with 0 additions and 114 deletions.
  1. +0 −7 Kconfig.zephyr
  2. +0 −94 arch/x86/core/ia32/crt0.S
  3. +0 −13 include/arch/x86/ia32/linker.ld
@@ -380,13 +380,6 @@ config BOOTLOADER_ESP_IDF
inside the build folder.
At flash time, the bootloader will be flashed with the zephyr image

config REALMODE
bool "boot from x86 real mode"
depends on X86
help
This option enabled Zephyr to start in x86 real mode, instead of
protected mode.

config BOOTLOADER_KEXEC
bool "Boot using Linux kexec() system call"
depends on X86
@@ -44,100 +44,6 @@
GTEXT(_sys_resume_from_deep_sleep)
#endif

#ifdef CONFIG_REALMODE

#define RM_CODE_SEG 0x8
#define RM_DATA_SEG 0x18
#define X86_CR0_PE 0x00000001
#define X86_CR0_WP 0x00010000
#define X86_CR4_PSE 0x00000010

.code16
.section ".boot", "ax"

.globl __jh_entry
__jh_entry:
lgdtl %cs:gdt_ptr

mov %cr0,%eax
or $X86_CR0_PE,%al
mov %eax,%cr0

ljmpl $RM_CODE_SEG,$start32

.code32
start32:
/*
* Minimal bootstrap into 32-bit mode, just to jump to
* __start
*/

/* 4Mb pages */
mov %cr4,%eax
or $X86_CR4_PSE,%eax
mov %eax,%cr4

/* Enable write protect and protected mode */
mov $(X86_CR0_WP | X86_CR0_PE),%eax
mov %eax,%cr0

movl $X86_MTRR_DEF_TYPE_MSR,%ecx
rdmsr
or $X86_MTRR_DEF_TYPE_MSR_ENABLE,%eax
wrmsr

mov $RM_DATA_SEG,%eax
mov %eax,%ds
mov %eax,%es
mov %eax,%ss

ljmp $RM_CODE_SEG, $__start

.global loader_gdt
loader_gdt:
.quad 0

/* Boot entry 1 (selector=0x0): 32-bit code descriptor: DPL0 */

.word 0xffff /* limit: xffff */
.word 0x0000 /* base : xxxx0000 */
.byte 0x00 /* base : xx00xxxx */
.byte 0x9b /* Accessed, Code e/r, Present, DPL0 */
.byte 0xcf /* limit: fxxxx, Page Gra, 32bit */
.byte 0x00 /* base : 00xxxxxx */

/* Boot entry 2 (selector=0x0): 16-bit code descriptor: DPL0 */

.word 0xffff /* limit: xffff */
.word 0x0000 /* base : xxxx0000 */
.byte 0x00 /* base : xx00xxxx */
.byte 0x9b /* Accessed, Code e/r, Present, DPL0 */
.byte 0x8f /* limit: fxxxx, Byte Gra, 16bit */
.byte 0x00 /* base : 00xxxxxx */

/* Boot entry 3 (selector=0x0): Data descriptor: DPL0 */

.word 0xffff /* limit: xffff */
.word 0x0000 /* base : xxxx0000 */
.byte 0x00 /* base : xx00xxxx */
.byte 0x93 /* Accessed, Data r/w, Present, DPL0 */
.byte 0xcf /* limit: fxxxx, Page Gra, 32bit */
.byte 0x00 /* base : 00xxxxxx */
gdt_ptr:
.short gdt_ptr - loader_gdt - 1
.long loader_gdt

.pushsection ".rodata"

.align(4096)

.popsection
#endif /* CONFIG_REALMODE */

/* processor is executing in 32-bit protected mode */

.balign 16,0x90

SECTION_FUNC(TEXT_START, __start)

#ifdef CONFIG_X86_MULTIBOOT_INFO
@@ -81,24 +81,11 @@ SECTIONS


GROUP_START(ROMABLE_REGION)
#ifdef CONFIG_REALMODE
/* 16-bit sections */
. = PHYS_RAM_ADDR;

SECTION_PROLOGUE(boot,,)
{
*(.boot)
. = ALIGN(16);
} GROUP_LINK_IN(ROMABLE_REGION)
#endif
. = ALIGN(8);

_image_rom_start = PHYS_LOAD_ADDR;
#ifndef CONFIG_REALMODE
_image_text_start = PHYS_LOAD_ADDR;
#else
_image_text_start = .;
#endif
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
{
. = CONFIG_TEXT_SECTION_OFFSET;

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