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boards: rv32m1_vega: Use different openocd config file for each core

Adds a new argument to the openocd runner to optionally specify the
config file. Updates the rv32m1_vega board to use different openocd
config files for the ri5cy and zero-riscy cores.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
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MaureenHelm authored and galak committed Apr 17, 2019
1 parent cf1d374 commit fe4b1ff0c3f8f952430e127052e19964f3518f20
@@ -1,4 +1,11 @@
# SPDX-License-Identifier: Apache-2.0

set(OPENOCD_USE_LOAD_IMAGE NO)

if(CONFIG_SOC_OPENISA_RV32M1_RI5CY)
board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_ri5cy.cfg")
elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY)
board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_zero_riscy.cfg")
endif()

include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
@@ -457,13 +457,13 @@ first make sure you're booting the right core.

1. In one terminal, use OpenOCD to connect to the board::

~/rv32m1-openocd -f boards/riscv32/rv32m1_vega/support/openocd.cfg
~/rv32m1-openocd -f boards/riscv32/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg

The output should look like this:

.. code-block:: none

$ ~/rv32m1-openocd -f boards/riscv32/rv32m1_vega/support/openocd.cfg
$ ~/rv32m1-openocd -f boards/riscv32/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg
Open On-Chip Debugger 0.10.0+dev-00431-ge1ec3c7d (2018-10-31-07:29)
[...]
Info : Listening on port 3333 for gdb connections
@@ -501,7 +501,7 @@ first make sure you're booting the right core.

In one cmd.exe prompt in the Zephyr directory::

C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\riscv32\rv32m1_vega\support\openocd.cfg
C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\riscv32\rv32m1_vega\support\openocd_rv32m1_vega_ri5cy.cfg

In a telnet program of your choice:

@@ -0,0 +1,115 @@
# Copyright 2018 NXP
# SPDX-License-Identifier: BSD-3-Clause

set _WORKAREASIZE 0x2000

adapter_khz 1000

interface jlink
transport select jtag

set _WORKAREASIZE 0x1000

set _CHIPNAME rv32m1

reset_config srst_only

# OpenCores Mohor JTAG TAP ID
set _CPUTAPID 0x249511C3

jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAME

# Select the TAP core we are using
tap_select mohor

# Select the debug unit core we are using. This debug unit as an option.

set ADBG_USE_HISPEED 1

# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
# on burst reads and writes to improve download speeds.
# This option must match the RTL configured option.

du_select adv [expr $ADBG_USE_HISPEED]

# Select core 1
core_select 1

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
$_TARGETNAME configure -event gdb-detach {
resume
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1

proc ri5cy_boot { } {

# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80

sleep 1000

mwb 0x40023000 0x70
mww 0x40023008 0xFFFF03FF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80

sleep 2
}

proc cm4_boot { } {

# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80

sleep 1000

mwb 0x40023000 0x70
mww 0x40023008 0xFFFFFFFF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80

sleep 2
}

proc zero_boot { } {

# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80

sleep 1000

mwb 0x40023000 0x70
mww 0x40023008 0xFFFF03BF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80

sleep 2
}

proc cm0_boot { } {

# Erase all blok unsecure
mwb 0x40023000 0x70
mww 0x40023004 0x49000000
mwb 0x40023000 0x80

sleep 1000

mwb 0x40023000 0x70
mww 0x40023008 0xFFFFFFBF
mww 0x40023004 0x43840000
mwb 0x40023000 0x80

sleep 2
}
@@ -18,13 +18,17 @@ class OpenOcdBinaryRunner(ZephyrBinaryRunner):

def __init__(self, cfg,
pre_cmd=None, load_cmd=None, verify_cmd=None, post_cmd=None,
tui=None,
tui=None, config=None,
tcl_port=DEFAULT_OPENOCD_TCL_PORT,
telnet_port=DEFAULT_OPENOCD_TELNET_PORT,
gdb_port=DEFAULT_OPENOCD_GDB_PORT):
super(OpenOcdBinaryRunner, self).__init__(cfg)
self.openocd_config = path.join(cfg.board_dir, 'support',
'openocd.cfg')

if config is not None:
self.openocd_config = config
else:
self.openocd_config = path.join(cfg.board_dir, 'support',
'openocd.cfg')

search_args = []
if cfg.openocd_search is not None:
@@ -47,6 +51,8 @@ def name(cls):

@classmethod
def do_add_parser(cls, parser):
parser.add_argument('--config',
help='if given, override default config file')
# Options for flashing:
parser.add_argument('--cmd-pre-load',
help='Command to run before flashing')
@@ -75,7 +81,7 @@ def create(cls, cfg, args):
cfg,
pre_cmd=args.cmd_pre_load, load_cmd=args.cmd_load,
verify_cmd=args.cmd_verify, post_cmd=args.cmd_post_verify,
tui=args.tui,
tui=args.tui, config=args.config,
tcl_port=args.tcl_port, telnet_port=args.telnet_port,
gdb_port=args.gdb_port)

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