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dts: bindings: sram: add SiFive dtim0 bindings

Add bindings for SiFive Data Tightly-Integrated Memory.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
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fkokosinski authored and MaureenHelm committed Apr 18, 2019
1 parent 4349281 commit ff1679950901e19273ff62735e2599f4c13bfe06
Showing with 28 additions and 0 deletions.
  1. +1 −0 CODEOWNERS
  2. +27 −0 dts/bindings/sram/sifive,dtim0.yaml
@@ -164,6 +164,7 @@
/dts/bindings/*/openisa* @MaureenHelm
/dts/bindings/*/st* @erwango
/dts/bindings/sensor/ams* @alexanderwachter
/dts/bindings/*/sifive* @mateusz-holenko @kgugala @pgielda @nategraff-sifive
/ext/fs/ @nashif @wentongwu
/ext/hal/atmel/asf/sam/include/same70*/ @aurel32
/ext/hal/atmel/asf/sam0/include/samr21/ @benpicco
@@ -0,0 +1,27 @@
#
# Copyright (c) 2019 Antmicro <www.antmicro.com>
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: Data Tightly-Integrated Memory
version: 0.1

description: >
This bindings describes the SiFive Data Tightly-Integrated Memory
properties:
compatible:
type: string
category: required
description: compatible strings
constraint: "sifive,dtim0"
generation: define

reg:
type: array
description: mmio register space
generation: define
category: required

...

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