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Branch: master
Commits on May 15, 2019
  1. boards: riscv32: add LiteX VexRiscV board

    fkokosinski authored and galak committed Mar 28, 2019
    Add LiteX VexRiscV board platform definitions and
    default configurations.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
  2. soc: riscv32: add LiteX VexRiscV SoC

    fkokosinski authored and galak committed Mar 28, 2019
    Add LiteX with softcore CPU VexRiscV SoC definitions and default
    configurations.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
  3. drivers: interrupt_controller: add LiteX interrupt controller driver

    fkokosinski authored and galak committed Mar 28, 2019
    Add LiteX interrupt controller driver and bindings for this device.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
  4. drivers: timer: add LiteX timer driver

    fkokosinski authored and galak committed Mar 28, 2019
    Add LiteX timer driver with bindings for this device.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
  5. drivers: serial: add LiteUART driver

    fkokosinski authored and galak committed Mar 28, 2019
    Add LiteX UART driver with bindings for this device.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Commits on May 10, 2019
  1. riscv32: use device tree defines in linker

    fkokosinski authored and MaureenHelm committed Apr 18, 2019
    Delete memory-related configs from defconfig and use device tree based
    macros in general riscv32 linker script instead of Kconfig ones.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
  2. soc: riscv32: sifive-freedom: soc.h: use defines from device tree

    fkokosinski authored and MaureenHelm committed Apr 30, 2019
    Use values generated from the device tree in RISCV_ROM_BASE,
    RISCV_ROM_SIZE, RISCV_RAM_BASE, RISCV_RAM_SIZE macros.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
  3. soc: riscv32: miv: soc.h: use defines from device tree

    fkokosinski authored and MaureenHelm committed May 7, 2019
    Use values generated from the device tree in RISCV_ROM_BASE,
    RISCV_ROM_SIZE, RISCV_RAM_BASE, RISCV_RAM_SIZE macros.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
  4. dts: riscv32: hifive1: add flash

    fkokosinski authored and MaureenHelm committed Apr 30, 2019
    Add flash to the SiFive HiFive1 device tree.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
  5. dts: riscv32: microsemi-miv: add flash and sram

    fkokosinski authored and MaureenHelm committed Apr 18, 2019
    Add flash and SRAM to the Microsemi MiV device tree.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
  6. dts: bindings: sram: add SiFive dtim0 bindings

    fkokosinski authored and MaureenHelm committed Apr 18, 2019
    Add bindings for SiFive Data Tightly-Integrated Memory.
    
    Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
    Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
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