Consistent feature dependency checks based on ARMvX-M

[carlescufi]

Introduce checks for the different ARMvX-M registers and features so that we make sure that they are not accidentally enabled by the users.
This includes VTOR, BASEPRI and all of the rest of the ARMvX-M features.

[ioannisg]

Core ARM registers in the different Cortex implementations:

1. VTOR register

• holds the vector table [offset] address
• Implementation:
  • Cortex M0: not present
  • Cortex M0+: optional
  • Cortex M3: present
  • Cortex M4: present
  • Cortex M23: optional
  • Cortex M33: present

2. BASEPRI register

• Base priority MASK register (masking out lower priorities)
• Implementation:
  • Cortex M0: not present
  • Cortex M0+: not present
  • Cortex M3: present
  • Cortex M4: present
  • Cortex M23: not present
  • Cortex M33: present

3. FAULTMASK register

• Fault priority MASK register (masking out exceptions other than NMI)
• Implementation:
  • Cortex M0: not present
  • Cortex M0+: not present
  • Cortex M3: present
  • Cortex M4: present
  • Cortex M23: not present
  • Cortex M33: present
  • Cortex M7: present

4. PRIMASK register

• Prevents activation of all exception with configurable priority
• Implementation: present in all Cores

5. CONTROL regsister

• controls the stack used when the processor is in Thread mode
• Implementation: present in all Cores

6. MSPLIM, PSPLIM registers

• Stack limit registers
• Implementation:
  • Cortex M0,M0+, M3, M4, M7: not present
  • Cortex M23: present only if Securtiy Extension is implemented
  • Cortex M33: present

[ioannisg]

Closing this (#6143) is reviewed and merged.