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STM32 SPI/I2S: LSB bit corrupted for the received data #9028

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avisconti opened this issue Jul 19, 2018 · 3 comments

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commented Jul 19, 2018

On ArgonKey board I have experimented a bug in I2S which at the end turned out to be a known bug (id-bug: SPI-031111). Basically, when the APB clock is fast and the SPI/I2S GPIOs are configured slow, the Least Significant Bit of SPI/I2S data can be corrupted. This issue impacts the following SoCs:
STM32F1, STM32L0, STM32L1, STM32F3x (some 64K and 256K variants), STM32F2, STM32F4, STM32F0x (some 64K and 32 K variant)).

I was able to solve this issue reducing APB clock to half speed and putting the I2S gpios to high_speed.
Concerning the gpio speed setting I would like to discuss with @erwango how to solve this properly. We can set for each family the SPI/I2S gpios to high_speed, but maybe fast_speed is enough depending whether the SoC vdd is 1V8 or 3V3 (1V8 requires a faster gpio response). So, I opened this Issue for a proper discussion.

Other possibility:
Instead of adding a fixed speed in each pinmux include file (like pinmux_stm32f4.h) we may want to keep it parametric and add a proper speed value in the pinmux.c of the BSP.

@nashif nashif added the bug label Jul 20, 2018

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commented Jul 20, 2018

I know that @mariotesi found the (maybe) same issue on SPI on Nucleo F411 with zephyr. Let's fix it properly.

avisconti added a commit to avisconti/zephyr that referenced this issue Jul 31, 2018

board: 96b_argonkey: Add on-board MP34DT05 microphone support in BSP
This commit is taking care of following stuff:

1. pinmux: STM32F4 micro is using I2S5_CK and I2S_SD to interface with
   on-board microphone.

2. default dts: make use of SPI5 because I2S is not currently supported
   in Zephyr dts bindings.

3. default configuration:
     - enable I2S5 and configure PLLI2S properly to generate
       I2SxCLK = 128MHz.
     - enable DMA

Note:
 As stated in issue zephyrproject-rtos#9028 we needed to take care of a known SPI/I2S bug
 implementing the following two actions:

 A. APB2 clock has been slowed down to 42MHz.
 B. The SPI/I2S clock gpio speed has been set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Jul 31, 2018

board: 96b_argonkey: Add on-board MP34DT05 microphone support in BSP
This commit is taking care of following stuff:

1. pinmux: STM32F4 micro is using I2S5_CK and I2S_SD to interface with
   on-board microphone.

2. default dts: make use of SPI5 because I2S is not currently supported
   in Zephyr dts bindings.

3. default configuration:
     - enable I2S5 and configure PLLI2S properly to generate
       I2SxCLK = 128MHz.
     - enable DMA

Note:
 As stated in issue zephyrproject-rtos#9028 we needed to take care of a known SPI/I2S bug
 implementing the following two actions:

 A. APB2 clock has been slowed down to 42MHz.
 B. The SPI/I2S clock gpio speed has been set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
@avisconti

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commented Jul 31, 2018

For ArgonKey board I included the fix to this issue in the PR #9183.

Two things has been done:
A. APB2 clock has been slowed down to 42MHz.
B. The SPI/I2S clock gpio speed has been set to very_high_speed.

@avisconti

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commented Aug 7, 2018

I'm closing now this issue.

@avisconti avisconti closed this Aug 7, 2018

avisconti added a commit to avisconti/zephyr that referenced this issue Oct 8, 2018

board: 96b_argonkey: Add on-board MP34DT05 microphone support in BSP
This commit is taking care of following stuff:

1. pinmux: STM32F4 micro is using I2S5_CK and I2S_SD to interface with
   on-board microphone.

2. default configuration:
     - enable I2S5 and configure PLLI2S properly to generate
       I2SxCLK = 128MHz.
     - enable DMA

Note:
 As stated in issue zephyrproject-rtos#9028 we needed to take care of a known SPI/I2S bug
 implementing the following two actions:

 A. APB2 clock has been slowed down to 42MHz.
 B. The SPI/I2S clock gpio speed has been set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Oct 8, 2018

board: 96b_argonkey: Add on-board MP34DT05 microphone support in BSP
This commit is taking care of following stuff:

1. pinmux: STM32F4 micro is using I2S5_CK and I2S_SD to interface with
   on-board microphone.

2. default configuration:
     - enable I2S5 and configure PLLI2S properly to generate
       I2SxCLK = 128MHz.
     - enable DMA

Note:
 As stated in issue zephyrproject-rtos#9028 we needed to take care of a known SPI/I2S bug
 implementing the following two actions:

 A. APB2 clock has been slowed down to 42MHz.
 B. The SPI/I2S clock gpio speed has been set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Oct 9, 2018

board: 96b_argonkey: Add on-board MP34DT05 microphone support in BSP
This commit is taking care of following stuff:

1. pinmux: STM32F4 micro is using I2S5_CK and I2S_SD to interface with
   on-board microphone.

2. default configuration:
     - enable I2S5 and configure PLLI2S properly to generate
       I2SxCLK = 128MHz.
     - enable DMA

Note:
 As stated in issue zephyrproject-rtos#9028 we needed to take care of a known SPI/I2S bug
 implementing the following two actions:

 A. APB2 clock has been slowed down to 42MHz.
 B. The SPI/I2S clock gpio speed has been set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Oct 9, 2018

board: 96b_argonkey: Add on-board MP34DT05 microphone support in BSP
This commit is taking care of following stuff:

1. pinmux: STM32F4 micro is using I2S5_CK and I2S_SD to interface with
   on-board microphone.

2. default configuration:
     - enable I2S5 and configure PLLI2S properly to generate
       I2SxCLK = 128MHz.
     - enable DMA

Note:
 As stated in issue zephyrproject-rtos#9028 we needed to take care of a known SPI/I2S bug
 implementing the following two actions:

 A. APB2 clock has been slowed down to 42MHz.
 B. The SPI/I2S clock gpio speed has been set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Oct 11, 2018

board: 96b_argonkey: Add on-board MP34DT05 microphone support in BSP
This commit is taking care of following stuff:

1. pinmux: STM32F4 micro is using I2S5_CK and I2S_SD to interface with
   on-board microphone.

2. default configuration:
     - enable I2S5 and configure PLLI2S properly to generate
       I2SxCLK = 128MHz.
     - enable DMA

Note:
 As stated in issue zephyrproject-rtos#9028 we needed to take care of a known SPI/I2S bug
 implementing the following two actions:

 A. APB2 clock has been slowed down to 42MHz.
 B. The SPI/I2S clock gpio speed has been set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Oct 11, 2018

board: 96b_argonkey: Add on-board MP34DT05 microphone support in BSP
This commit is taking care of following stuff:

1. pinmux: STM32F4 micro is using I2S5_CK and I2S_SD to interface with
   on-board microphone.

2. default configuration:
     - enable I2S5 and configure PLLI2S properly to generate
       I2SxCLK = 128MHz.
     - enable DMA

Note:
 As stated in issue zephyrproject-rtos#9028 we needed to take care of a known SPI/I2S bug
 implementing the following two actions:

 A. APB2 clock has been slowed down to 42MHz.
 B. The SPI/I2S clock gpio speed has been set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

nashif added a commit that referenced this issue Oct 11, 2018

board: 96b_argonkey: Add on-board MP34DT05 microphone support in BSP
This commit is taking care of following stuff:

1. pinmux: STM32F4 micro is using I2S5_CK and I2S_SD to interface with
   on-board microphone.

2. default configuration:
     - enable I2S5 and configure PLLI2S properly to generate
       I2SxCLK = 128MHz.
     - enable DMA

Note:
 As stated in issue #9028 we needed to take care of a known SPI/I2S bug
 implementing the following two actions:

 A. APB2 clock has been slowed down to 42MHz.
 B. The SPI/I2S clock gpio speed has been set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Feb 1, 2019

boards: nucleo_f401re: Fix issue zephyrproject-rtos#9028
As stated in issue zephyrproject-rtos#9028 we need to take care of a known SPI/I2S bug
implementing the following two actions:

A. APB2 clock must be slowed down to 42MHz.
B. The SPI/I2S clock/data gpio speed must set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Feb 1, 2019

boards: nucleo_f401re: Fix issue zephyrproject-rtos#9028
As stated in issue zephyrproject-rtos#9028 we need to take care of a known SPI/I2S bug
implementing the following two actions:

A. APB2 clock must be slowed down to 42MHz.
B. The SPI/I2S clock/data gpio speed must set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Feb 1, 2019

boards: nucleo_f401re: Fix issue zephyrproject-rtos#9028
As stated in issue zephyrproject-rtos#9028 we need to take care of a known SPI/I2S bug
implementing the following two actions:

A. APB2 clock must be slowed down to 42MHz.
B. The SPI/I2S clock/data gpio speed must set to very_high_speed.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Feb 6, 2019

drivers/pinmux: stm32: (FIX) Force very_high speed to SPIx_SCK gpio
Fix issue zephyrproject-rtos#9028: last bit of SPI/I2S transaction may be corrupted.
Impacted STM32 SOC series: F0/F1/F2/F3/F4/L0.

Notes:
- F2/F4/L0: set gpio to very_high speed ('11')
- F0/F3: set gpio to high speed ('11').
- F1: set gpio to 50MHz.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Feb 6, 2019

drivers/pinmux: stm32: (FIX) Force very_high speed to SPIx_SCK gpio
Fix issue zephyrproject-rtos#9028: last bit of SPI/I2S transaction may be corrupted.
Impacted STM32 SOC series: F0/F1/F2/F3/F4/L0.

Notes:
- F2/F4/L0: set gpio to very_high speed ('11')
- F0/F3: set gpio to high speed ('11').
- F1: set gpio to 50MHz.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

galak added a commit that referenced this issue Feb 7, 2019

drivers/pinmux: stm32: (FIX) Force very_high speed to SPIx_SCK gpio
Fix issue #9028: last bit of SPI/I2S transaction may be corrupted.
Impacted STM32 SOC series: F0/F1/F2/F3/F4/L0.

Notes:
- F2/F4/L0: set gpio to very_high speed ('11')
- F0/F3: set gpio to high speed ('11').
- F1: set gpio to 50MHz.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

avisconti added a commit to avisconti/zephyr that referenced this issue Feb 8, 2019

drivers/pinmux: stm32: (FIX) Force very_high speed to SPIx_SCK gpio
Fix issue zephyrproject-rtos#9028: last bit of SPI/I2S transaction may be corrupted.
Impacted STM32 SOC series: F0/F1/F2/F3/F4/L0.

Notes:
- F2/F4/L0: set gpio to very_high speed ('11')
- F0/F3: set gpio to high speed ('11').
- F1: set gpio to 50MHz.

Signed-off-by: Armando Visconti <armando.visconti@st.com>

Mani-Sadhasivam added a commit to Mani-Sadhasivam/zephyr that referenced this issue Mar 18, 2019

pinmux: stm32f4: Add STM32_OSPEEDR_VERY_HIGH_SPEED to pinmux header
Since STM32_OSPEEDR_VERY_HIGH_SPEED flag is required for all I2S_CK
pins, lets add this to the STM32F4 pinmux header and remove the
duplicates in board files. While we are at it, let's add the missing
pinmux definitions for I2S_2 also.

Fixes: zephyrproject-rtos#9028

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

galak added a commit to Mani-Sadhasivam/zephyr that referenced this issue Apr 17, 2019

pinmux: stm32f4: Add STM32_OSPEEDR_VERY_HIGH_SPEED to pinmux header
Since STM32_OSPEEDR_VERY_HIGH_SPEED flag is required for all I2S_CK
pins, lets add this to the STM32F4 pinmux header and remove the
duplicates in board files. While we are at it, let's add the missing
pinmux definitions for I2S_2 also.

Fixes: zephyrproject-rtos#9028

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Mani-Sadhasivam added a commit to Mani-Sadhasivam/zephyr that referenced this issue Apr 19, 2019

pinmux: stm32f4: Add STM32_OSPEEDR_VERY_HIGH_SPEED to pinmux header
Since STM32_OSPEEDR_VERY_HIGH_SPEED flag is required for all I2S_CK
pins, lets add this to the STM32F4 pinmux header and remove the
duplicates in board files. While we are at it, let's add the missing
pinmux definitions for I2S_2 also.

Fixes: zephyrproject-rtos#9028

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

galak added a commit that referenced this issue Apr 26, 2019

pinmux: stm32f4: Add STM32_OSPEEDR_VERY_HIGH_SPEED to pinmux header
Since STM32_OSPEEDR_VERY_HIGH_SPEED flag is required for all I2S_CK
pins, lets add this to the STM32F4 pinmux header and remove the
duplicates in board files. While we are at it, let's add the missing
pinmux definitions for I2S_2 also.

Fixes: #9028

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

nashif added a commit that referenced this issue May 3, 2019

pinmux: stm32f4: Add STM32_OSPEEDR_VERY_HIGH_SPEED to pinmux header
Since STM32_OSPEEDR_VERY_HIGH_SPEED flag is required for all I2S_CK
pins, lets add this to the STM32F4 pinmux header and remove the
duplicates in board files. While we are at it, let's add the missing
pinmux definitions for I2S_2 also.

Fixes: #9028

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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