diff --git a/arch/arc/CMakeLists.txt b/arch/arc/CMakeLists.txt
index 8135d072f10b5..66f4848e23d22 100644
--- a/arch/arc/CMakeLists.txt
+++ b/arch/arc/CMakeLists.txt
@@ -12,8 +12,11 @@ zephyr_cc_option(-fno-delete-null-pointer-checks)
 
 zephyr_cc_option_ifdef(CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS -munaligned-access)
 
-# Instruct compiler to use register R26 as thread pointer
-# for thread local storage.
-zephyr_cc_option_ifdef(CONFIG_THREAD_LOCAL_STORAGE -mtp-regno=26)
+if(CONFIG_ISA_ARCV2)
+  # Instruct compiler to use register R26 as thread pointer
+  # for thread local storage.
+  # For ARCv3 the register is fixed to r30, so we don't need to specify it
+  zephyr_cc_option_ifdef(CONFIG_THREAD_LOCAL_STORAGE -mtp-regno=26)
+endif()
 
 add_subdirectory(core)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 12cf0970ca7bd..49e6d19ae8cf2 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -39,6 +39,11 @@ config ISA_ARCV2
 	help
 	  v2 ISA for the ARC-HS & ARC-EM cores
 
+config ISA_ARCV3
+	bool "ARC ISA v3"
+	select USE_SWITCH
+	select USE_SWITCH_SUPPORTED
+
 endchoice
 
 if ISA_ARCV2
@@ -83,11 +88,34 @@ config CPU_HS3X
 
 endif #ISA_ARCV2
 
+if ISA_ARCV3
+
+config CPU_HS6X
+	bool
+	select CPU_ARCHS
+	select 64BIT
+	help
+	  If y, the SoC uses an ARC HS6x CPU
+
+endif #ISA_ARCV3
+
 config FP_FPU_DA
 	bool
 
 menu "ARC CPU Options"
 
+config ARC_HAS_ZOL
+	bool
+	depends on ISA_ARCV2
+	default y
+	help
+	  ARCv2 CPUs have ZOL hardware loop mechanism which the ARCv3 ISA drops.
+	  Architecturally ZOL provides
+	  - LPcc instruction
+	  - LP_COUNT core reg
+	  - LP_START, LP_END aux regs
+	  Disabling this option removes usage of ZOL regs from code
+
 config NUM_IRQ_PRIO_LEVELS
 	int "Number of supported interrupt priority levels"
 	range 1 16
@@ -123,6 +151,7 @@ config RGF_NUM_BANKS
 
 config ARC_FIRQ
 	bool "FIRQ enable"
+	depends on ISA_ARCV2
 	default y
 	help
 	  Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts
@@ -147,6 +176,7 @@ config ARC_FIRQ_STACK_SIZE
 
 config ARC_HAS_STACK_CHECKING
 	bool "ARC has STACK_CHECKING"
+	depends on ISA_ARCV2
 	default y
 	help
 	  ARC is configured with STACK_CHECKING which is a mechanism for
@@ -233,6 +263,7 @@ config ARC_HAS_ACCL_REGS
 
 config ARC_HAS_SECURE
 	bool "ARC has SecureShield"
+	depends on ISA_ARCV2
 	select CPU_HAS_TEE
 	select ARCH_HAS_TRUSTED_EXECUTION
 	help
@@ -320,3 +351,15 @@ config ARC_EXCEPTION_DEBUG
 	  strings.
 
 endmenu
+
+config MAIN_STACK_SIZE
+	default 4096 if 64BIT
+
+config TEST_EXTRA_STACKSIZE
+	default 1024 if 64BIT
+
+config CMSIS_THREAD_MAX_STACK_SIZE
+	default 1024 if 64BIT
+
+config CMSIS_V2_THREAD_MAX_STACK_SIZE
+	default 1024 if 64BIT
diff --git a/arch/arc/core/cpu_idle.S b/arch/arc/core/cpu_idle.S
index d1bb0bd85f679..25183ad9441c2 100644
--- a/arch/arc/core/cpu_idle.S
+++ b/arch/arc/core/cpu_idle.S
@@ -16,6 +16,7 @@
 #include <toolchain.h>
 #include <linker/sections.h>
 #include <arch/cpu.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 GTEXT(arch_cpu_idle)
 GTEXT(arch_cpu_atomic_idle)
@@ -36,11 +37,12 @@ SECTION_VAR(BSS, z_arc_cpu_sleep_mode)
 SECTION_FUNC(TEXT, arch_cpu_idle)
 
 #ifdef CONFIG_TRACING
-	push_s blink
+	PUSHR blink
 	jl    sys_trace_idle
-	pop_s blink
+	POPR blink
 #endif
 
+	/* z_arc_cpu_sleep_mode is 32 bit despite of platform bittnes */
 	ld r1, [z_arc_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
@@ -57,11 +59,12 @@ SECTION_FUNC(TEXT, arch_cpu_idle)
 SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
 
 #ifdef CONFIG_TRACING
-	push_s blink
+	PUSHR blink
 	jl    sys_trace_idle
-	pop_s blink
+	POPR blink
 #endif
 
+	/* z_arc_cpu_sleep_mode is 32 bit despite of platform bittnes */
 	ld r1, [z_arc_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
diff --git a/arch/arc/core/fatal.c b/arch/arc/core/fatal.c
index 31d56fc1060d7..829f71a09bcf2 100644
--- a/arch/arc/core/fatal.c
+++ b/arch/arc/core/fatal.c
@@ -24,17 +24,19 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 #ifdef CONFIG_ARC_EXCEPTION_DEBUG
 static void dump_arc_esf(const z_arch_esf_t *esf)
 {
-	LOG_ERR(" r0: 0x%08x  r1: 0x%08x  r2: 0x%08x  r3: 0x%08x",
+	LOG_ERR(" r0: 0x%" PRIxPTR "  r1: 0x%" PRIxPTR "  r2: 0x%" PRIxPTR "  r3: 0x%" PRIxPTR "",
 		esf->r0, esf->r1, esf->r2, esf->r3);
-	LOG_ERR(" r4: 0x%08x  r5: 0x%08x  r6: 0x%08x  r7: 0x%08x",
+	LOG_ERR(" r4: 0x%" PRIxPTR "  r5: 0x%" PRIxPTR "  r6: 0x%" PRIxPTR "  r7: 0x%" PRIxPTR "",
 		esf->r4, esf->r5, esf->r6, esf->r7);
-	LOG_ERR(" r8: 0x%08x  r9: 0x%08x r10: 0x%08x r11: 0x%08x",
+	LOG_ERR(" r8: 0x%" PRIxPTR "  r9: 0x%" PRIxPTR " r10: 0x%" PRIxPTR " r11: 0x%" PRIxPTR "",
 		esf->r8, esf->r9, esf->r10, esf->r11);
-	LOG_ERR("r12: 0x%08x r13: 0x%08x  pc: 0x%08x",
+	LOG_ERR("r12: 0x%" PRIxPTR " r13: 0x%" PRIxPTR "  pc: 0x%" PRIxPTR "",
 		esf->r12, esf->r13, esf->pc);
-	LOG_ERR(" blink: 0x%08x status32: 0x%08x", esf->blink, esf->status32);
-	LOG_ERR("lp_end: 0x%08x lp_start: 0x%08x lp_count: 0x%08x",
+	LOG_ERR(" blink: 0x%" PRIxPTR " status32: 0x%" PRIxPTR "", esf->blink, esf->status32);
+#ifdef CONFIG_ARC_HAS_ZOL
+	LOG_ERR("lp_end: 0x%" PRIxPTR " lp_start: 0x%" PRIxPTR " lp_count: 0x%" PRIxPTR "",
 		esf->lp_end, esf->lp_start, esf->lp_count);
+#endif /* CONFIG_ARC_HAS_ZOL */
 }
 #endif
 
diff --git a/arch/arc/core/fault_s.S b/arch/arc/core/fault_s.S
index 5285f9a5ed36a..297c935714e38 100644
--- a/arch/arc/core/fault_s.S
+++ b/arch/arc/core/fault_s.S
@@ -17,6 +17,7 @@
 #include <arch/cpu.h>
 #include <swap_macros.h>
 #include <syscall.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 GTEXT(_Fault)
 GTEXT(__reset)
@@ -43,10 +44,10 @@ GTEXT(z_irq_do_offload);
 	lr r0,[_ARC_V2_ERSEC_STAT]
 	st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
 #endif
-	lr r0,[_ARC_V2_ERET]
-	st_s r0, [sp, ___isf_t_pc_OFFSET]
-	lr r0,[_ARC_V2_ERSTATUS]
-	st_s r0, [sp, ___isf_t_status32_OFFSET]
+	LRR r0, [_ARC_V2_ERET]
+	STR r0, sp, ___isf_t_pc_OFFSET
+	LRR r0, [_ARC_V2_ERSTATUS]
+	STR r0, sp, ___isf_t_status32_OFFSET
 .endm
 
 /*
@@ -84,9 +85,9 @@ _exc_entry:
 	 * and exception is raised, then here it's guaranteed that
 	 * exception handling has necessary stack to use
 	 */
-	mov ilink, sp
+	MOVR ilink, sp
 	_get_curr_cpu_irq_stack sp
-	sub sp, sp, (CONFIG_ISR_STACK_SIZE - CONFIG_ARC_EXCEPTION_STACK_SIZE)
+	SUBR sp, sp, (CONFIG_ISR_STACK_SIZE - CONFIG_ARC_EXCEPTION_STACK_SIZE)
 
 	/*
 	 * save caller saved registers
@@ -102,9 +103,9 @@ _exc_entry:
 	_save_exc_regs_into_stack
 
 	/* sp is parameter of _Fault */
-	mov_s r0, sp
+	MOVR r0, sp
 	/* ilink is the thread's original sp */
-	mov r1, ilink
+	MOVR r1, ilink
 	jl _Fault
 
 _exc_return:
@@ -118,9 +119,9 @@ _exc_return:
 
 	_get_next_switch_handle
 
-	breq r0, r2, _exc_return_from_exc
+	BREQR r0, r2, _exc_return_from_exc
 
-	mov_s r2, r0
+	MOVR r2, r0
 
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	/*
@@ -145,8 +146,8 @@ _exc_return:
 	 */
 	mov ilink, r2
 #endif
-	lr r3, [_ARC_V2_STATUS32]
-	and r3,r3,(~(_ARC_V2_STATUS32_AE | _ARC_V2_STATUS32_RB(7)))
+	LRR r3, [_ARC_V2_STATUS32]
+	ANDR r3, r3, (~(_ARC_V2_STATUS32_AE | _ARC_V2_STATUS32_RB(7)))
 	kflag r3
 	/* pretend lowest priority interrupt happened to use common handler
 	 * if exception is raised in irq, i.e., _ARC_V2_AUX_IRQ_ACT !=0,
@@ -158,7 +159,7 @@ _exc_return:
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	mov_s r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
 #else
-	mov_s r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
+	MOVR r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
 #endif
 
 #ifdef CONFIG_ARC_NORMAL_FIRMWARE
@@ -169,7 +170,7 @@ _exc_return:
 	sjli SJLI_CALL_ARC_SECURE
 	pop_s r2
 #else
-	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+	SRR r3, [_ARC_V2_AUX_IRQ_ACT]
 #endif
 
 #if defined(CONFIG_ARC_FIRQ) && CONFIG_RGF_NUM_BANKS != 1
@@ -183,18 +184,18 @@ _exc_return_from_exc:
 	/* exception handler may change return address.
 	 * reload it
 	 */
-	ld_s r0, [sp, ___isf_t_pc_OFFSET]
-	sr r0, [_ARC_V2_ERET]
+	LDR r0, sp, ___isf_t_pc_OFFSET
+	SRR r0, [_ARC_V2_ERET]
 
 	_pop_irq_stack_frame
-	mov sp, ilink
+	MOVR sp, ilink
 	rtie
 
 /* separated entry for trap which may be used by irq_offload, USERPSACE */
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	/* get the id of trap_s */
-	lr ilink, [_ARC_V2_ECR]
-	and ilink, ilink, 0x3f
+	LRR ilink, [_ARC_V2_ECR]
+	ANDR ilink, ilink, 0x3f
 #ifdef CONFIG_USERSPACE
 	cmp ilink, _TRAP_S_CALL_SYSTEM_CALL
 	bne _do_non_syscall_trap
@@ -236,7 +237,7 @@ _do_non_syscall_trap:
 	 * so its entry is different with normal exception handling, it is
 	 * handled in isr stack
 	 */
-	cmp ilink, _TRAP_S_SCALL_IRQ_OFFLOAD
+	CMPR ilink, _TRAP_S_SCALL_IRQ_OFFLOAD
 	bne _exc_entry
 	/* save caller saved registers */
 	_create_irq_stack_frame
@@ -247,15 +248,15 @@ _do_non_syscall_trap:
 	_check_and_inc_int_nest_counter r0, r1
 
 	bne.d exc_nest_handle
-	mov_s r0, sp
+	MOVR r0, sp
 
 	_get_curr_cpu_irq_stack sp
 exc_nest_handle:
-	push_s r0
+	PUSHR r0
 
 	jl z_irq_do_offload
 
-	pop sp
+	POPR sp
 
 	_dec_int_nest_counter r0, r1
 
diff --git a/arch/arc/core/isr_wrapper.S b/arch/arc/core/isr_wrapper.S
index 344402c4dfb70..d285748a2ac1c 100644
--- a/arch/arc/core/isr_wrapper.S
+++ b/arch/arc/core/isr_wrapper.S
@@ -20,6 +20,7 @@
 #include <kernel_structs.h>
 #include <arch/cpu.h>
 #include <swap_macros.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 GTEXT(_isr_wrapper)
 GTEXT(_isr_demux)
@@ -238,8 +239,8 @@ rirq_path:
 	j_s [r2]
 #endif
 #else
-	mov_s r3, _rirq_exit
-	mov_s r2, _rirq_enter
+	MOVR r3, _rirq_exit
+	MOVR r2, _rirq_enter
 	j_s [r2]
 #endif
 
@@ -247,14 +248,15 @@ rirq_path:
 .macro exit_tickless_idle
 #if defined(CONFIG_PM)
 	clri r0 /* do not interrupt exiting tickless idle operations */
-	mov_s r1, _kernel
+	MOVR r1, _kernel
+	/* z_kernel.idle is 32 bit despite of platform bittnes */
 	ld_s r3, [r1, _kernel_offset_to_idle] /* requested idle duration */
 	breq r3, 0, _skip_pm_save_idle_exit
 
 	st 0, [r1, _kernel_offset_to_idle] /* zero idle duration */
-	push_s blink
+	PUSHR blink
 	jl z_pm_save_idle_exit
-	pop_s blink
+	POPR blink
 
 _skip_pm_save_idle_exit:
 	seti r0
@@ -263,16 +265,16 @@ _skip_pm_save_idle_exit:
 
 /* when getting here, r3 contains the interrupt exit stub to call */
 SECTION_FUNC(TEXT, _isr_demux)
-	push_s r3
+	PUSHR r3
 
 /* according to ARCv2 ISA, r25, r30, r58, r59 are caller-saved
  * scratch registers, possibly used by interrupt handlers
  */
-	push r25
-	push r30
+	PUSHR r25
+	PUSHR r30
 #ifdef CONFIG_ARC_HAS_ACCL_REGS
-	push r58
-	push r59
+	PUSHR r58
+	PUSHR r59
 #endif
 
 #ifdef CONFIG_TRACING_ISR
@@ -290,26 +292,30 @@ irq_hint_handled:
 
 	sub r0, r0, 16
 
-	mov_s r1, _sw_isr_table
-	add3 r0, r1, r0   /* table entries are 8-bytes wide */
-
-	ld_s r1, [r0, 4] /* ISR into r1 */
+	MOVR r1, _sw_isr_table
+	/* SW ISR table entries are 8-bytes wide for 32bit ISA and
+	 * 16-bytes wide for 64bit ISA */
+	ASLR r0, r0, (ARC_REGSHIFT + 1)
+	ADDR r0, r1, r0
+	/* ISR into r1 */
+	LDR r1, r0, ARC_REGSZ
 	jl_s.d [r1]
-	ld_s r0, [r0] /* delay slot: ISR parameter into r0  */
+	/* delay slot: ISR parameter into r0 */
+	LDR r0, r0
 
 #ifdef CONFIG_TRACING_ISR
 	bl sys_trace_isr_exit
 #endif
 
 #ifdef CONFIG_ARC_HAS_ACCL_REGS
-	pop r59
-	pop r58
+	POPR r59
+	POPR r58
 #endif
 
-	pop r30
-	pop r25
+	POPR r30
+	POPR r25
 
 	/* back from ISR, jump to exit stub */
-	pop_s r3
+	POPR r3
 	j_s [r3]
 	nop_s
diff --git a/arch/arc/core/offsets/offsets.c b/arch/arc/core/offsets/offsets.c
index 23736f9336211..07222bef61213 100644
--- a/arch/arc/core/offsets/offsets.c
+++ b/arch/arc/core/offsets/offsets.c
@@ -58,9 +58,11 @@ GEN_OFFSET_SYM(_isf_t, r11);
 GEN_OFFSET_SYM(_isf_t, r12);
 GEN_OFFSET_SYM(_isf_t, r13);
 GEN_OFFSET_SYM(_isf_t, blink);
+#ifdef CONFIG_ARC_HAS_ZOL
 GEN_OFFSET_SYM(_isf_t, lp_end);
 GEN_OFFSET_SYM(_isf_t, lp_start);
 GEN_OFFSET_SYM(_isf_t, lp_count);
+#endif /* CONFIG_ARC_HAS_ZOL */
 #ifdef CONFIG_CODE_DENSITY
 GEN_OFFSET_SYM(_isf_t, ei_base);
 GEN_OFFSET_SYM(_isf_t, ldi_base);
diff --git a/arch/arc/core/regular_irq.S b/arch/arc/core/regular_irq.S
index b3d9601efe8c9..1008594d3741c 100644
--- a/arch/arc/core/regular_irq.S
+++ b/arch/arc/core/regular_irq.S
@@ -20,6 +20,7 @@
 #include <linker/sections.h>
 #include <arch/cpu.h>
 #include <swap_macros.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 GTEXT(_rirq_enter)
 GTEXT(_rirq_exit)
@@ -216,11 +217,11 @@ SECTION_FUNC(TEXT, _rirq_enter)
 	_check_and_inc_int_nest_counter r0, r1
 
 	bne.d rirq_nest
-	mov_s r0, sp
+	MOVR r0, sp
 
 	_get_curr_cpu_irq_stack sp
 rirq_nest:
-	push_s r0
+	PUSHR r0
 
 	seti
 	j _isr_demux
@@ -236,7 +237,7 @@ rirq_nest:
 SECTION_FUNC(TEXT, _rirq_exit)
 	clri
 
-	pop sp
+	POPR sp
 
 	_dec_int_nest_counter r0, r1
 
@@ -251,7 +252,7 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	 */
 	_get_next_switch_handle
 
-	cmp r0, r2
+	CMPR r0, r2
 	beq _rirq_no_switch
 
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
@@ -263,10 +264,11 @@ SECTION_FUNC(TEXT, _rirq_exit)
 	/* r2 is old thread */
 	_irq_store_old_thread_callee_regs
 
-	st _CAUSE_RIRQ, [r2, _thread_offset_to_relinquish_cause]
+	/* _thread_arch.relinquish_cause is 32 bit despite of platform bittnes */
+	_st32_huge_offset _CAUSE_RIRQ, r2, _thread_offset_to_relinquish_cause, r2
 
 	/* mov new thread (r0) to r2 */
-	mov r2, r0
+	MOVR r2, r0
 
 /* _rirq_newthread_switch required by exception handling */
 .align 4
@@ -295,11 +297,13 @@ _rirq_switch_from_coop:
 	 */
 
 	/* carve fake stack */
-	sub sp, sp, ___isf_t_pc_OFFSET
+	SUBR sp, sp, ___isf_t_pc_OFFSET
 
 
+#ifdef CONFIG_ARC_HAS_ZOL
 	/* reset zero-overhead loops */
-	st 0, [sp, ___isf_t_lp_end_OFFSET]
+	STR 0, sp, ___isf_t_lp_end_OFFSET
+#endif /* CONFIG_ARC_HAS_ZOL */
 
 	/*
 	 * r13 is part of both the callee and caller-saved register sets because
@@ -307,14 +311,14 @@ _rirq_switch_from_coop:
 	 * IRQ prologue. r13 thus has to be set to its correct value in the IRQ
 	 * stack frame.
 	 */
-	st_s r13, [sp, ___isf_t_r13_OFFSET]
+	STR r13, sp, ___isf_t_r13_OFFSET
 
 #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
-	push_s blink
+	PUSHR blink
 
 	bl z_thread_mark_switched_in
 
-	pop_s blink
+	POPR blink
 #endif
 	/* stack now has the IRQ stack frame layout, pointing to sp */
 	/* rtie will pop the rest from the stack */
@@ -327,11 +331,11 @@ _rirq_switch_from_rirq:
 	_set_misc_regs_irq_switch_from_irq
 
 #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
-	push_s blink
+	PUSHR blink
 
 	bl z_thread_mark_switched_in
 
-	pop_s blink
+	POPR blink
 #endif
 _rirq_no_switch:
 	rtie
diff --git a/arch/arc/core/reset.S b/arch/arc/core/reset.S
index 7905eeb886c41..4445f29a3e23c 100644
--- a/arch/arc/core/reset.S
+++ b/arch/arc/core/reset.S
@@ -15,6 +15,7 @@
 #include <linker/sections.h>
 #include <arch/cpu.h>
 #include <swap_macros.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 GDATA(z_interrupt_stacks)
 GDATA(z_main_stack)
@@ -76,11 +77,11 @@ SECTION_FUNC(TEXT,__start)
 	/* set the vector table base early,
 	 * so that exception vectors can be handled.
 	 */
-	mov_s r0, _VectorTable
+	MOVR r0, _VectorTable
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	sr r0, [_ARC_V2_IRQ_VECT_BASE_S]
 #else
-	sr r0, [_ARC_V2_IRQ_VECT_BASE]
+	SRR r0, [_ARC_V2_IRQ_VECT_BASE]
 #endif
 
 	lr r0, [_ARC_V2_STATUS32]
diff --git a/arch/arc/core/switch.S b/arch/arc/core/switch.S
index 8e6ecf030305f..f458f884067df 100644
--- a/arch/arc/core/switch.S
+++ b/arch/arc/core/switch.S
@@ -21,6 +21,7 @@
 #include <arch/cpu.h>
 #include <v2/irq.h>
 #include <swap_macros.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 GTEXT(z_arc_switch)
 
@@ -60,17 +61,17 @@ SECTION_FUNC(TEXT, z_arc_switch)
 	 * get old_thread from r1
 	 */
 
-	sub r2, r1, ___thread_t_switch_handle_OFFSET
+	SUBR r2, r1, ___thread_t_switch_handle_OFFSET
 
-
-	st _CAUSE_COOP, [r2, _thread_offset_to_relinquish_cause]
+	/* _thread_arch.relinquish_cause is 32 bit despite of platform bittnes */
+	_st32_huge_offset _CAUSE_COOP, r2, _thread_offset_to_relinquish_cause, r3
 
 	/*
 	 * Save status32 and blink on the stack before the callee-saved registers.
 	 * This is the same layout as the start of an IRQ stack frame.
 	 */
-	lr r3, [_ARC_V2_STATUS32]
-	push_s r3
+	LRR r3, [_ARC_V2_STATUS32]
+	PUSHR r3
 
 #ifdef CONFIG_ARC_HAS_SECURE
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
@@ -81,7 +82,7 @@ SECTION_FUNC(TEXT, z_arc_switch)
 	push_s r3
 #endif
 
-	push_s blink
+	PUSHR blink
 
 	_store_old_thread_callee_regs
 
@@ -90,7 +91,7 @@ SECTION_FUNC(TEXT, z_arc_switch)
  */
 	_disable_stack_checking r3
 
-	mov_s r2, r0
+	MOVR r2, r0
 
 	_load_new_thread_callee_regs
 
@@ -104,22 +105,22 @@ SECTION_FUNC(TEXT, z_arc_switch)
 .align 4
 _switch_return_from_coop:
 
-	pop_s blink /* pc into blink */
+	POPR blink /* pc into blink */
 #ifdef CONFIG_ARC_HAS_SECURE
 	pop_s r3    /* pop SEC_STAT */
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	sflag r3
 #endif
 #endif
-	pop_s r3    /* status32 into r3 */
+	POPR r3    /* status32 into r3 */
 	kflag r3    /* write status32 */
 
 #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
-	push_s blink
+	PUSHR blink
 
 	bl z_thread_mark_switched_in
 
-	pop_s blink
+	POPR blink
 #endif
 	j_s [blink]
 
@@ -135,11 +136,11 @@ _switch_return_from_firq:
 	 * thread
 	 */
 
-	lr r3, [_ARC_V2_AUX_IRQ_ACT]
+	LRR r3, [_ARC_V2_AUX_IRQ_ACT]
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	or r3, r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
 #else
-	or r3, r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
+	ORR r3, r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
 #endif
 
 #ifdef CONFIG_ARC_NORMAL_FIRMWARE
@@ -148,13 +149,13 @@ _switch_return_from_firq:
 	mov_s r6, ARC_S_CALL_AUX_WRITE
 	sjli SJLI_CALL_ARC_SECURE
 #else
-	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+	SRR r3, [_ARC_V2_AUX_IRQ_ACT]
 #endif
 #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
-	push_s blink
+	PUSHR blink
 
 	bl z_thread_mark_switched_in
 
-	pop_s blink
+	POPR blink
 #endif
 	rtie
diff --git a/arch/arc/core/thread.c b/arch/arc/core/thread.c
index 0cf26ffae397f..be3b4052111d3 100644
--- a/arch/arc/core/thread.c
+++ b/arch/arc/core/thread.c
@@ -22,15 +22,15 @@
 
 /*  initial stack frame */
 struct init_stack_frame {
-	uint32_t pc;
+	uintptr_t pc;
 #ifdef CONFIG_ARC_HAS_SECURE
 	uint32_t sec_stat;
 #endif
-	uint32_t status32;
-	uint32_t r3;
-	uint32_t r2;
-	uint32_t r1;
-	uint32_t r0;
+	uintptr_t status32;
+	uintptr_t r3;
+	uintptr_t r2;
+	uintptr_t r1;
+	uintptr_t r0;
 };
 
 #ifdef CONFIG_USERSPACE
@@ -122,8 +122,13 @@ static inline void arch_setup_callee_saved_regs(struct k_thread *thread,
 	ARG_UNUSED(regs);
 
 #ifdef CONFIG_THREAD_LOCAL_STORAGE
-	/* R26 is used for thread pointer */
+#ifdef CONFIG_ISA_ARCV2
+	/* R26 is used for thread pointer for ARCv2 */
 	regs->r26 = thread->tls;
+#else
+	/* R30 is used for thread pointer for ARCv3 */
+	regs->r30 = thread->tls;
+#endif /* CONFIG_ISA_ARCV2 */
 #endif
 }
 
@@ -158,15 +163,15 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	}
 #else
 	iframe->status32 = _ARC_V2_STATUS32_DZ;
-	iframe->pc = ((uint32_t)z_thread_entry_wrapper);
+	iframe->pc = ((uintptr_t)z_thread_entry_wrapper);
 #endif /* CONFIG_USERSPACE */
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	iframe->sec_stat = z_arc_v2_aux_reg_read(_ARC_V2_SEC_STAT);
 #endif
-	iframe->r0 = (uint32_t)entry;
-	iframe->r1 = (uint32_t)p1;
-	iframe->r2 = (uint32_t)p2;
-	iframe->r3 = (uint32_t)p3;
+	iframe->r0 = (uintptr_t)entry;
+	iframe->r1 = (uintptr_t)p1;
+	iframe->r2 = (uintptr_t)p2;
+	iframe->r3 = (uintptr_t)p3;
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
@@ -182,7 +187,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	thread->switch_handle = thread;
 	thread->arch.relinquish_cause = _CAUSE_COOP;
 	thread->callee_saved.sp =
-		(uint32_t)iframe - ___callee_saved_stack_t_SIZEOF;
+		(uintptr_t)iframe - ___callee_saved_stack_t_SIZEOF;
 
 	arch_setup_callee_saved_regs(thread, thread->callee_saved.sp);
 
diff --git a/arch/arc/core/thread_entry_wrapper.S b/arch/arc/core/thread_entry_wrapper.S
index f0e79d9010f90..b738bc944fe20 100644
--- a/arch/arc/core/thread_entry_wrapper.S
+++ b/arch/arc/core/thread_entry_wrapper.S
@@ -14,6 +14,7 @@
 #include <toolchain.h>
 #include <linker/sections.h>
 #include <v2/irq.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 GTEXT(z_thread_entry_wrapper)
 GTEXT(z_thread_entry_wrapper1)
@@ -30,9 +31,9 @@ GTEXT(z_thread_entry_wrapper1)
 SECTION_FUNC(TEXT, z_thread_entry_wrapper)
 	seti _ARC_V2_INIT_IRQ_LOCK_KEY
 z_thread_entry_wrapper1:
-	pop_s r3
-	pop_s r2
-	pop_s r1
-	pop_s r0
+	POPR r3
+	POPR r2
+	POPR r1
+	POPR r0
 	j z_thread_entry
 	nop
diff --git a/arch/arc/core/vector_table.c b/arch/arc/core/vector_table.c
index 9f85f3c837834..a165d6b68779f 100644
--- a/arch/arc/core/vector_table.c
+++ b/arch/arc/core/vector_table.c
@@ -28,39 +28,40 @@
 #include "vector_table.h"
 
 struct vector_table {
-	uint32_t reset;
-	uint32_t memory_error;
-	uint32_t instruction_error;
-	uint32_t ev_machine_check;
-	uint32_t ev_tlb_miss_i;
-	uint32_t ev_tlb_miss_d;
-	uint32_t ev_prot_v;
-	uint32_t ev_privilege_v;
-	uint32_t ev_swi;
-	uint32_t ev_trap;
-	uint32_t ev_extension;
-	uint32_t ev_div_zero;
-	uint32_t ev_dc_error;
-	uint32_t ev_maligned;
-	uint32_t unused_1;
-	uint32_t unused_2;
+	uintptr_t reset;
+	uintptr_t memory_error;
+	uintptr_t instruction_error;
+	uintptr_t ev_machine_check;
+	uintptr_t ev_tlb_miss_i;
+	uintptr_t ev_tlb_miss_d;
+	uintptr_t ev_prot_v;
+	uintptr_t ev_privilege_v;
+	uintptr_t ev_swi;
+	uintptr_t ev_trap;
+	uintptr_t ev_extension;
+	uintptr_t ev_div_zero;
+	/* ev_dc_error is unused in ARCv3 and de-facto unused in ARCv2 as well */
+	uintptr_t ev_dc_error;
+	uintptr_t ev_maligned;
+	uintptr_t unused_1;
+	uintptr_t unused_2;
 };
 
 struct vector_table _VectorTable Z_GENERIC_SECTION(.exc_vector_table) = {
-	(uint32_t)__reset,
-	(uint32_t)__memory_error,
-	(uint32_t)__instruction_error,
-	(uint32_t)__ev_machine_check,
-	(uint32_t)__ev_tlb_miss_i,
-	(uint32_t)__ev_tlb_miss_d,
-	(uint32_t)__ev_prot_v,
-	(uint32_t)__ev_privilege_v,
-	(uint32_t)__ev_swi,
-	(uint32_t)__ev_trap,
-	(uint32_t)__ev_extension,
-	(uint32_t)__ev_div_zero,
-	(uint32_t)__ev_dc_error,
-	(uint32_t)__ev_maligned,
+	(uintptr_t)__reset,
+	(uintptr_t)__memory_error,
+	(uintptr_t)__instruction_error,
+	(uintptr_t)__ev_machine_check,
+	(uintptr_t)__ev_tlb_miss_i,
+	(uintptr_t)__ev_tlb_miss_d,
+	(uintptr_t)__ev_prot_v,
+	(uintptr_t)__ev_privilege_v,
+	(uintptr_t)__ev_swi,
+	(uintptr_t)__ev_trap,
+	(uintptr_t)__ev_extension,
+	(uintptr_t)__ev_div_zero,
+	(uintptr_t)__ev_dc_error,
+	(uintptr_t)__ev_maligned,
 	0,
 	0
 };
diff --git a/arch/arc/include/kernel_arch_data.h b/arch/arc/include/kernel_arch_data.h
index 49b1cd7708de7..94c5f9f126ecc 100644
--- a/arch/arc/include/kernel_arch_data.h
+++ b/arch/arc/include/kernel_arch_data.h
@@ -37,70 +37,74 @@ extern "C" {
 
 #ifdef CONFIG_ARC_HAS_SECURE
 struct _irq_stack_frame {
-	uint32_t lp_end;
-	uint32_t lp_start;
-	uint32_t lp_count;
+#ifdef CONFIG_ARC_HAS_ZOL
+	uintptr_t lp_end;
+	uintptr_t lp_start;
+	uintptr_t lp_count;
+#endif /* CONFIG_ARC_HAS_ZOL */
 #ifdef CONFIG_CODE_DENSITY
 	/*
 	 * Currently unsupported. This is where those registers are
 	 * automatically pushed on the stack by the CPU when taking a regular
 	 * IRQ.
 	 */
-	uint32_t ei_base;
-	uint32_t ldi_base;
-	uint32_t jli_base;
+	uintptr_t ei_base;
+	uintptr_t ldi_base;
+	uintptr_t jli_base;
 #endif
-	uint32_t r0;
-	uint32_t r1;
-	uint32_t r2;
-	uint32_t r3;
-	uint32_t r4;
-	uint32_t r5;
-	uint32_t r6;
-	uint32_t r7;
-	uint32_t r8;
-	uint32_t r9;
-	uint32_t r10;
-	uint32_t r11;
-	uint32_t r12;
-	uint32_t r13;
-	uint32_t blink;
-	uint32_t pc;
-	uint32_t sec_stat;
-	uint32_t status32;
+	uintptr_t r0;
+	uintptr_t r1;
+	uintptr_t r2;
+	uintptr_t r3;
+	uintptr_t r4;
+	uintptr_t r5;
+	uintptr_t r6;
+	uintptr_t r7;
+	uintptr_t r8;
+	uintptr_t r9;
+	uintptr_t r10;
+	uintptr_t r11;
+	uintptr_t r12;
+	uintptr_t r13;
+	uintptr_t blink;
+	uintptr_t pc;
+	uintptr_t sec_stat;
+	uintptr_t status32;
 };
 #else
 struct _irq_stack_frame {
-	uint32_t r0;
-	uint32_t r1;
-	uint32_t r2;
-	uint32_t r3;
-	uint32_t r4;
-	uint32_t r5;
-	uint32_t r6;
-	uint32_t r7;
-	uint32_t r8;
-	uint32_t r9;
-	uint32_t r10;
-	uint32_t r11;
-	uint32_t r12;
-	uint32_t r13;
-	uint32_t blink;
-	uint32_t lp_end;
-	uint32_t lp_start;
-	uint32_t lp_count;
+	uintptr_t r0;
+	uintptr_t r1;
+	uintptr_t r2;
+	uintptr_t r3;
+	uintptr_t r4;
+	uintptr_t r5;
+	uintptr_t r6;
+	uintptr_t r7;
+	uintptr_t r8;
+	uintptr_t r9;
+	uintptr_t r10;
+	uintptr_t r11;
+	uintptr_t r12;
+	uintptr_t r13;
+	uintptr_t blink;
+#ifdef CONFIG_ARC_HAS_ZOL
+	uintptr_t lp_end;
+	uintptr_t lp_start;
+	uintptr_t lp_count;
+#endif /* CONFIG_ARC_HAS_ZOL */
 #ifdef CONFIG_CODE_DENSITY
 	/*
 	 * Currently unsupported. This is where those registers are
 	 * automatically pushed on the stack by the CPU when taking a regular
 	 * IRQ.
 	 */
-	uint32_t ei_base;
-	uint32_t ldi_base;
-	uint32_t jli_base;
+	uintptr_t ei_base;
+	uintptr_t ldi_base;
+	uintptr_t jli_base;
 #endif
-	uint32_t pc;
-	uint32_t status32;
+	uintptr_t pc;
+	uintptr_t status32;
 };
 #endif
 
@@ -110,47 +114,47 @@ typedef struct _irq_stack_frame _isf_t;
 
 /* callee-saved registers pushed on the stack, not in k_thread */
 struct _callee_saved_stack {
-	uint32_t r13;
-	uint32_t r14;
-	uint32_t r15;
-	uint32_t r16;
-	uint32_t r17;
-	uint32_t r18;
-	uint32_t r19;
-	uint32_t r20;
-	uint32_t r21;
-	uint32_t r22;
-	uint32_t r23;
-	uint32_t r24;
-	uint32_t r25;
-	uint32_t r26;
-	uint32_t fp; /* r27 */
+	uintptr_t r13;
+	uintptr_t r14;
+	uintptr_t r15;
+	uintptr_t r16;
+	uintptr_t r17;
+	uintptr_t r18;
+	uintptr_t r19;
+	uintptr_t r20;
+	uintptr_t r21;
+	uintptr_t r22;
+	uintptr_t r23;
+	uintptr_t r24;
+	uintptr_t r25;
+	uintptr_t r26;
+	uintptr_t fp; /* r27 */
 
 #ifdef CONFIG_USERSPACE
 #ifdef CONFIG_ARC_HAS_SECURE
-	uint32_t user_sp;
-	uint32_t kernel_sp;
+	uintptr_t user_sp;
+	uintptr_t kernel_sp;
 #else
-	uint32_t user_sp;
+	uintptr_t user_sp;
 #endif
 #endif
 	/* r28 is the stack pointer and saved separately */
 	/* r29 is ILINK and does not need to be saved */
-	uint32_t r30;
+	uintptr_t r30;
 
 #ifdef CONFIG_ARC_HAS_ACCL_REGS
-	uint32_t r58;
-	uint32_t r59;
+	uintptr_t r58;
+	uintptr_t r59;
 #endif
 
 #ifdef CONFIG_FPU_SHARING
-	uint32_t fpu_status;
-	uint32_t fpu_ctrl;
+	uintptr_t fpu_status;
+	uintptr_t fpu_ctrl;
 #ifdef CONFIG_FP_FPU_DA
-	uint32_t dpfp2h;
-	uint32_t dpfp2l;
-	uint32_t dpfp1h;
-	uint32_t dpfp1l;
+	uintptr_t dpfp2h;
+	uintptr_t dpfp2l;
+	uintptr_t dpfp1h;
+	uintptr_t dpfp1l;
 #endif
 
 #endif
diff --git a/arch/arc/include/kernel_arch_func.h b/arch/arc/include/kernel_arch_func.h
index 84c37bf39b59f..0c12f7b27b922 100644
--- a/arch/arc/include/kernel_arch_func.h
+++ b/arch/arc/include/kernel_arch_func.h
@@ -24,9 +24,7 @@
 
 #include <kernel_arch_data.h>
 
-#ifdef CONFIG_ISA_ARCV2
 #include <v2/irq.h>
-#endif
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/arch/arc/include/swap_macros.h b/arch/arc/include/swap_macros.h
index dbffcce3a3602..558e594844807 100644
--- a/arch/arc/include/swap_macros.h
+++ b/arch/arc/include/swap_macros.h
@@ -14,30 +14,31 @@
 #include <toolchain.h>
 #include <arch/cpu.h>
 #include <arch/arc/tool-compat.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 #ifdef _ASMLANGUAGE
 
 /* save callee regs of current thread in r2 */
 .macro _save_callee_saved_regs
 
-	sub_s sp, sp, ___callee_saved_stack_t_SIZEOF
+	SUBR sp, sp, ___callee_saved_stack_t_SIZEOF
 
 	/* save regs on stack */
-	st_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
-	st_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
-	st_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
-	st r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
-	st r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
-	st r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
-	st r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
-	st r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
-	st r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
-	st r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
-	st r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
-	st r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
-	st r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
-	st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
-	st fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
+	STR r13, sp, ___callee_saved_stack_t_r13_OFFSET
+	STR r14, sp, ___callee_saved_stack_t_r14_OFFSET
+	STR r15, sp, ___callee_saved_stack_t_r15_OFFSET
+	STR r16, sp, ___callee_saved_stack_t_r16_OFFSET
+	STR r17, sp, ___callee_saved_stack_t_r17_OFFSET
+	STR r18, sp, ___callee_saved_stack_t_r18_OFFSET
+	STR r19, sp, ___callee_saved_stack_t_r19_OFFSET
+	STR r20, sp, ___callee_saved_stack_t_r20_OFFSET
+	STR r21, sp, ___callee_saved_stack_t_r21_OFFSET
+	STR r22, sp, ___callee_saved_stack_t_r22_OFFSET
+	STR r23, sp, ___callee_saved_stack_t_r23_OFFSET
+	STR r24, sp, ___callee_saved_stack_t_r24_OFFSET
+	STR r25, sp, ___callee_saved_stack_t_r25_OFFSET
+	STR r26, sp, ___callee_saved_stack_t_r26_OFFSET
+	STR fp,  sp, ___callee_saved_stack_t_fp_OFFSET
 
 #ifdef CONFIG_USERSPACE
 #ifdef CONFIG_ARC_HAS_SECURE
@@ -57,11 +58,11 @@
 	st_s r13, [sp, ___callee_saved_stack_t_user_sp_OFFSET]
 #endif
 #endif
-	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
+	STR r30, sp, ___callee_saved_stack_t_r30_OFFSET
 
 #ifdef CONFIG_ARC_HAS_ACCL_REGS
-	st r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
-	st r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
+	STR r58, sp, ___callee_saved_stack_t_r58_OFFSET
+	STR r59, sp, ___callee_saved_stack_t_r59_OFFSET
 #endif
 
 #ifdef CONFIG_FPU_SHARING
@@ -87,17 +88,17 @@
 #endif
 
 	/* save stack pointer in struct k_thread */
-	st sp, [r2, _thread_offset_to_sp]
+	STR sp, r2, _thread_offset_to_sp
 .endm
 
 /* load the callee regs of thread (in r2)*/
 .macro _load_callee_saved_regs
 	/* restore stack pointer from struct k_thread */
-	ld sp, [r2, _thread_offset_to_sp]
+	LDR sp, r2, _thread_offset_to_sp
 
 #ifdef CONFIG_ARC_HAS_ACCL_REGS
-	ld r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
-	ld r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
+	LDR r58, sp, ___callee_saved_stack_t_r58_OFFSET
+	LDR r59, sp, ___callee_saved_stack_t_r59_OFFSET
 #endif
 
 #ifdef CONFIG_FPU_SHARING
@@ -142,30 +143,30 @@
 #endif
 #endif
 
-	ld_s r13, [sp, ___callee_saved_stack_t_r13_OFFSET]
-	ld_s r14, [sp, ___callee_saved_stack_t_r14_OFFSET]
-	ld_s r15, [sp, ___callee_saved_stack_t_r15_OFFSET]
-	ld r16, [sp, ___callee_saved_stack_t_r16_OFFSET]
-	ld r17, [sp, ___callee_saved_stack_t_r17_OFFSET]
-	ld r18, [sp, ___callee_saved_stack_t_r18_OFFSET]
-	ld r19, [sp, ___callee_saved_stack_t_r19_OFFSET]
-	ld r20, [sp, ___callee_saved_stack_t_r20_OFFSET]
-	ld r21, [sp, ___callee_saved_stack_t_r21_OFFSET]
-	ld r22, [sp, ___callee_saved_stack_t_r22_OFFSET]
-	ld r23, [sp, ___callee_saved_stack_t_r23_OFFSET]
-	ld r24, [sp, ___callee_saved_stack_t_r24_OFFSET]
-	ld r25, [sp, ___callee_saved_stack_t_r25_OFFSET]
-	ld r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
-	ld fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
-	ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
-
-	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
+	LDR r13, sp, ___callee_saved_stack_t_r13_OFFSET
+	LDR r14, sp, ___callee_saved_stack_t_r14_OFFSET
+	LDR r15, sp, ___callee_saved_stack_t_r15_OFFSET
+	LDR r16, sp, ___callee_saved_stack_t_r16_OFFSET
+	LDR r17, sp, ___callee_saved_stack_t_r17_OFFSET
+	LDR r18, sp, ___callee_saved_stack_t_r18_OFFSET
+	LDR r19, sp, ___callee_saved_stack_t_r19_OFFSET
+	LDR r20, sp, ___callee_saved_stack_t_r20_OFFSET
+	LDR r21, sp, ___callee_saved_stack_t_r21_OFFSET
+	LDR r22, sp, ___callee_saved_stack_t_r22_OFFSET
+	LDR r23, sp, ___callee_saved_stack_t_r23_OFFSET
+	LDR r24, sp, ___callee_saved_stack_t_r24_OFFSET
+	LDR r25, sp, ___callee_saved_stack_t_r25_OFFSET
+	LDR r26, sp, ___callee_saved_stack_t_r26_OFFSET
+	LDR fp,  sp, ___callee_saved_stack_t_fp_OFFSET
+	LDR r30, sp, ___callee_saved_stack_t_r30_OFFSET
+
+	ADDR sp, sp, ___callee_saved_stack_t_SIZEOF
 
 .endm
 
 /* discard callee regs */
 .macro _discard_callee_saved_regs
-	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
+	ADDR sp, sp, ___callee_saved_stack_t_SIZEOF
 .endm
 
 /*
@@ -174,33 +175,35 @@
  */
 .macro _create_irq_stack_frame
 
-	sub_s sp, sp, ___isf_t_SIZEOF
+	SUBR sp, sp, ___isf_t_SIZEOF
 
-	st blink, [sp, ___isf_t_blink_OFFSET]
+	STR blink, sp, ___isf_t_blink_OFFSET
 
 	/* store these right away so we can use them if needed */
 
-	st_s r13, [sp, ___isf_t_r13_OFFSET]
-	st_s r12, [sp, ___isf_t_r12_OFFSET]
-	st   r11, [sp, ___isf_t_r11_OFFSET]
-	st   r10, [sp, ___isf_t_r10_OFFSET]
-	st   r9,  [sp, ___isf_t_r9_OFFSET]
-	st   r8,  [sp, ___isf_t_r8_OFFSET]
-	st   r7,  [sp, ___isf_t_r7_OFFSET]
-	st   r6,  [sp, ___isf_t_r6_OFFSET]
-	st   r5,  [sp, ___isf_t_r5_OFFSET]
-	st   r4,  [sp, ___isf_t_r4_OFFSET]
-	st_s r3,  [sp, ___isf_t_r3_OFFSET]
-	st_s r2,  [sp, ___isf_t_r2_OFFSET]
-	st_s r1,  [sp, ___isf_t_r1_OFFSET]
-	st_s r0,  [sp, ___isf_t_r0_OFFSET]
-
-	mov r0, lp_count
-	st_s r0, [sp, ___isf_t_lp_count_OFFSET]
-	lr r1, [_ARC_V2_LP_START]
-	lr r0, [_ARC_V2_LP_END]
-	st_s r1, [sp, ___isf_t_lp_start_OFFSET]
-	st_s r0, [sp, ___isf_t_lp_end_OFFSET]
+	STR r13, sp, ___isf_t_r13_OFFSET
+	STR r12, sp, ___isf_t_r12_OFFSET
+	STR r11, sp, ___isf_t_r11_OFFSET
+	STR r10, sp, ___isf_t_r10_OFFSET
+	STR r9,  sp, ___isf_t_r9_OFFSET
+	STR r8,  sp, ___isf_t_r8_OFFSET
+	STR r7,  sp, ___isf_t_r7_OFFSET
+	STR r6,  sp, ___isf_t_r6_OFFSET
+	STR r5,  sp, ___isf_t_r5_OFFSET
+	STR r4,  sp, ___isf_t_r4_OFFSET
+	STR r3,  sp, ___isf_t_r3_OFFSET
+	STR r2,  sp, ___isf_t_r2_OFFSET
+	STR r1,  sp, ___isf_t_r1_OFFSET
+	STR r0,  sp, ___isf_t_r0_OFFSET
+
+#ifdef CONFIG_ARC_HAS_ZOL
+	MOVR r0, lp_count
+	STR r0, sp, ___isf_t_lp_count_OFFSET
+	LRR r1, [_ARC_V2_LP_START]
+	LRR r0, [_ARC_V2_LP_END]
+	STR r1, sp, ___isf_t_lp_start_OFFSET
+	STR r0, sp, ___isf_t_lp_end_OFFSET
+#endif /* CONFIG_ARC_HAS_ZOL */
 
 #ifdef CONFIG_CODE_DENSITY
 	lr r1, [_ARC_V2_JLI_BASE]
@@ -219,7 +222,7 @@
  */
 .macro _pop_irq_stack_frame
 
-	ld blink, [sp, ___isf_t_blink_OFFSET]
+	LDR blink, sp, ___isf_t_blink_OFFSET
 
 #ifdef CONFIG_CODE_DENSITY
 	ld_s r1, [sp, ___isf_t_jli_base_OFFSET]
@@ -230,27 +233,29 @@
 	sr r2, [_ARC_V2_EI_BASE]
 #endif
 
-	ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
-	mov lp_count, r0
-	ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
-	ld_s r0, [sp, ___isf_t_lp_end_OFFSET]
-	sr r1, [_ARC_V2_LP_START]
-	sr r0, [_ARC_V2_LP_END]
-
-	ld_s r13, [sp, ___isf_t_r13_OFFSET]
-	ld_s r12, [sp, ___isf_t_r12_OFFSET]
-	ld   r11, [sp, ___isf_t_r11_OFFSET]
-	ld   r10, [sp, ___isf_t_r10_OFFSET]
-	ld   r9,  [sp, ___isf_t_r9_OFFSET]
-	ld   r8,  [sp, ___isf_t_r8_OFFSET]
-	ld   r7,  [sp, ___isf_t_r7_OFFSET]
-	ld   r6,  [sp, ___isf_t_r6_OFFSET]
-	ld   r5,  [sp, ___isf_t_r5_OFFSET]
-	ld   r4,  [sp, ___isf_t_r4_OFFSET]
-	ld_s r3,  [sp, ___isf_t_r3_OFFSET]
-	ld_s r2,  [sp, ___isf_t_r2_OFFSET]
-	ld_s r1,  [sp, ___isf_t_r1_OFFSET]
-	ld_s r0,  [sp, ___isf_t_r0_OFFSET]
+#ifdef CONFIG_ARC_HAS_ZOL
+	LDR r0, sp, ___isf_t_lp_count_OFFSET
+	MOVR lp_count, r0
+	LDR r1, sp, ___isf_t_lp_start_OFFSET
+	LDR r0, sp, ___isf_t_lp_end_OFFSET
+	SRR r1, [_ARC_V2_LP_START]
+	SRR r0, [_ARC_V2_LP_END]
+#endif /* CONFIG_ARC_HAS_ZOL */
+
+	LDR r13, sp, ___isf_t_r13_OFFSET
+	LDR r12, sp, ___isf_t_r12_OFFSET
+	LDR r11, sp, ___isf_t_r11_OFFSET
+	LDR r10, sp, ___isf_t_r10_OFFSET
+	LDR r9,  sp, ___isf_t_r9_OFFSET
+	LDR r8,  sp, ___isf_t_r8_OFFSET
+	LDR r7,  sp, ___isf_t_r7_OFFSET
+	LDR r6,  sp, ___isf_t_r6_OFFSET
+	LDR r5,  sp, ___isf_t_r5_OFFSET
+	LDR r4,  sp, ___isf_t_r4_OFFSET
+	LDR r3,  sp, ___isf_t_r3_OFFSET
+	LDR r2,  sp, ___isf_t_r2_OFFSET
+	LDR r1,  sp, ___isf_t_r1_OFFSET
+	LDR r0,  sp, ___isf_t_r0_OFFSET
 
 
 	/*
@@ -262,7 +267,7 @@
 	 * status32 differently depending on the execution context they are
 	 * running in (arch_switch(), firq or exception).
 	 */
-	add_s sp, sp, ___isf_t_SIZEOF
+	ADDR sp, sp, ___isf_t_SIZEOF
 
 .endm
 
@@ -307,7 +312,8 @@
 	ld.as MACRO_ARG(reg1), [_curr_cpu, MACRO_ARG(reg1)]
 	ld MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET]
 #else
-	mov MACRO_ARG(reg1), _kernel
+	MOVR MACRO_ARG(reg1), _kernel
+	/* z_kernel.nested is 32 bit despite of platform bittnes */
 	ld MACRO_ARG(reg2), [MACRO_ARG(reg1), _kernel_offset_to_nested]
 #endif
 	add MACRO_ARG(reg2), MACRO_ARG(reg2), 1
@@ -329,7 +335,8 @@
 	ld.as MACRO_ARG(reg1), [_curr_cpu, MACRO_ARG(reg1)]
 	ld MACRO_ARG(reg2), [MACRO_ARG(reg1), ___cpu_t_nested_OFFSET]
 #else
-	mov MACRO_ARG(reg1), _kernel
+	MOVR MACRO_ARG(reg1), _kernel
+	/* z_kernel.nested is 32 bit despite of platform bittnes */
 	ld MACRO_ARG(reg2), [MACRO_ARG(reg1), _kernel_offset_to_nested]
 #endif
 	sub MACRO_ARG(reg2), MACRO_ARG(reg2), 1
@@ -374,21 +381,21 @@
 	ld.as MACRO_ARG(irq_sp), [_curr_cpu, MACRO_ARG(irq_sp)]
 	ld MACRO_ARG(irq_sp), [MACRO_ARG(irq_sp), ___cpu_t_irq_stack_OFFSET]
 #else
-	mov MACRO_ARG(irq_sp), _kernel
-	ld MACRO_ARG(irq_sp), [MACRO_ARG(irq_sp), _kernel_offset_to_irq_stack]
+	MOVR MACRO_ARG(irq_sp), _kernel
+	LDR MACRO_ARG(irq_sp), MACRO_ARG(irq_sp), _kernel_offset_to_irq_stack
 #endif
 .endm
 
 /* macro to push aux reg through reg */
 .macro PUSHAX, reg, aux
-	lr MACRO_ARG(reg), [MACRO_ARG(aux)]
-	st.a MACRO_ARG(reg), [sp, -4]
+	LRR MACRO_ARG(reg), [MACRO_ARG(aux)]
+	PUSHR MACRO_ARG(reg)
 .endm
 
 /* macro to pop aux reg through reg */
 .macro POPAX, reg, aux
-	ld.ab MACRO_ARG(reg), [sp, 4]
-	sr MACRO_ARG(reg), [MACRO_ARG(aux)]
+	POPR MACRO_ARG(reg)
+	SRR MACRO_ARG(reg), [MACRO_ARG(aux)]
 .endm
 
 
@@ -443,7 +450,7 @@
 	bl configure_mpu_thread
 	pop_s r2
 #endif
-
+	/* _thread_arch.relinquish_cause is 32 bit despite of platform bittnes */
 	ld r3, [r2, _thread_offset_to_relinquish_cause]
 .endm
 
@@ -479,10 +486,10 @@
 
 /* macro to get next switch handle in assembly */
 .macro _get_next_switch_handle
-	push_s r2
-	mov r0, sp
+	PUSHR r2
+	MOVR r0, sp
 	bl z_arch_get_next_switch_handle
-	pop_s  r2
+	POPR  r2
 .endm
 
 /* macro to disable stack checking in assembly, need a GPR
@@ -520,6 +527,19 @@
 #endif
 .endm
 
+/*
+ * When we accessing bloated struct member we can exceed u9 operand in store
+ * instruction. So we can use _st32_huge_offset macro instead
+ */
+.macro _st32_huge_offset, d, s, off, temp
+	.if MACRO_ARG(off) > 255 || MACRO_ARG(off) < -256
+		ADDR MACRO_ARG(temp), MACRO_ARG(s), MACRO_ARG(off)
+		st MACRO_ARG(d), [MACRO_ARG(temp)]
+	.else
+		st MACRO_ARG(d), [MACRO_ARG(s), MACRO_ARG(off)]
+	.endif
+.endm
+
 #endif /* _ASMLANGUAGE */
 
 #endif /*  ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_ */
diff --git a/arch/arc/include/v2/irq.h b/arch/arc/include/v2/irq.h
index 1f2a1a63deb56..4bdd20be74ccc 100644
--- a/arch/arc/include/v2/irq.h
+++ b/arch/arc/include/v2/irq.h
@@ -54,7 +54,9 @@ extern "C" {
 static ALWAYS_INLINE void z_irq_setup(void)
 {
 	uint32_t aux_irq_ctrl_value = (
+#ifdef CONFIG_ARC_HAS_ZOL
 		_ARC_V2_AUX_IRQ_CTRL_LOOP_REGS | /* save lp_xxx registers */
+#endif /* CONFIG_ARC_HAS_ZOL */
 #ifdef CONFIG_CODE_DENSITY
 		_ARC_V2_AUX_IRQ_CTRL_LP | /* save code density registers */
 #endif
diff --git a/boards/arc/nsim/board.cmake b/boards/arc/nsim/board.cmake
index e58a7beb9de61..cbd65a1145313 100644
--- a/boards/arc/nsim/board.cmake
+++ b/boards/arc/nsim/board.cmake
@@ -20,6 +20,9 @@ board_runner_args(arc-nsim "--props=nsim_hs.props")
 board_runner_args(mdb-nsim "--nsim_args=mdb_hs.args")
 elseif(${CONFIG_SOC_NSIM_HS_SMP})
 board_runner_args(mdb-nsim "--cores=${CONFIG_MP_NUM_CPUS}" "--nsim_args=mdb_hs_smp.args")
+elseif(${CONFIG_SOC_NSIM_HS6X})
+board_runner_args(arc-nsim "--props=nsim_hs6x.props")
+board_runner_args(mdb-nsim "--nsim_args=mdb_hs6x.args")
 endif()
 
 board_finalize_runner_args(arc-nsim)
diff --git a/boards/arc/nsim/nsim_hs6x.dts b/boards/arc/nsim/nsim_hs6x.dts
new file mode 100644
index 0000000000000..17525cdedec6a
--- /dev/null
+++ b/boards/arc/nsim/nsim_hs6x.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "nsim.dtsi"
+
+/ {
+	model = "snps,nsim_hs";
+	compatible = "snps,nsim_hs";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,archs";
+			reg = <0>;
+		};
+	};
+};
diff --git a/boards/arc/nsim/nsim_hs6x.yaml b/boards/arc/nsim/nsim_hs6x.yaml
new file mode 100644
index 0000000000000..79aeec867b052
--- /dev/null
+++ b/boards/arc/nsim/nsim_hs6x.yaml
@@ -0,0 +1,11 @@
+identifier: nsim_hs6x
+name: HS6x nSIM simulator
+type: mcu
+simulation: nsim
+arch: arc
+toolchain:
+  - cross-compile
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
diff --git a/boards/arc/nsim/nsim_hs6x_defconfig b/boards/arc/nsim/nsim_hs6x_defconfig
new file mode 100644
index 0000000000000..c2fc96d9119e6
--- /dev/null
+++ b/boards/arc/nsim/nsim_hs6x_defconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ISA_ARCV3=y
+CONFIG_SOC_NSIM=y
+CONFIG_SOC_NSIM_HS6X=y
+CONFIG_BOARD_NSIM=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_XIP=n
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_PRINTK=y
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_ARC_EXCEPTION_DEBUG=y
diff --git a/boards/arc/nsim/support/mdb_hs6x.args b/boards/arc/nsim/support/mdb_hs6x.args
new file mode 100644
index 0000000000000..0b9984a33d9d5
--- /dev/null
+++ b/boards/arc/nsim/support/mdb_hs6x.args
@@ -0,0 +1,18 @@
+	-arc64
+	-nogoifmain
+	-Xatomic
+	-Xtimer0
+	-Xtimer1
+	-Xdiv_rem
+	-Xunaligned
+	-prop=nsim_isa_addr_size=64
+	-prop=nsim_isa_pc_size=64
+	-prop=nsim_isa_vec64=1
+	-dcache=65536,64,2,a
+	-dcache_feature=2
+	-dcache_uncached_region
+	-dcache_mem_cycles=2
+	-icache=65536,64,4,a
+	-icache_feature=2
+	-noprofile
+	-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
diff --git a/boards/arc/nsim/support/nsim_hs6x.props b/boards/arc/nsim/support/nsim_hs6x.props
new file mode 100644
index 0000000000000..4949908e211ab
--- /dev/null
+++ b/boards/arc/nsim/support/nsim_hs6x.props
@@ -0,0 +1,29 @@
+	maxlastpc=0
+	trace_enabled=0
+	nsim_isa_family=arc64
+	nsim_isa_core=1
+	arcver=113
+	nsim_isa_atomic_option=1
+	nsim_isa_shift_option=3
+	nsim_isa_code_density_option=2
+	nsim_isa_div_rem_option=2
+	nsim_isa_swap_option=1
+	nsim_isa_bitscan_option=1
+	nsim_isa_enable_timer_0=1
+	nsim_isa_enable_timer_1=1
+	nsim_isa_has_interrupts=1
+	nsim_isa_dual_issue_option=1
+	nsim_isa_div64_option=1
+	nsim_isa_mpy64=1
+	nsim_isa_mpy_option=9
+	nsim_isa_addr_size=64
+	nsim_isa_pc_size=64
+	nsim_isa_vec64=1
+	dcache=65536,64,2,a
+	nsim_isa_dc_version=5
+	nsim_isa_dc_feature_level=2
+	nsim_isa_dc_mem_cycles=1
+	icache=65536,64,4,a
+	nsim_isa_ic_version=6
+	nsim_isa_ic_feature_level=2
+	nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
diff --git a/boards/arc/qemu_arc/board.cmake b/boards/arc/qemu_arc/board.cmake
index 1f0205acdd76c..515a9efc93777 100644
--- a/boards/arc/qemu_arc/board.cmake
+++ b/boards/arc/qemu_arc/board.cmake
@@ -8,10 +8,20 @@ set(QEMU_FLAGS_${ARCH} -cpu arcem)
 elseif(${CONFIG_SOC_QEMU_ARC_HS})
 set(QEMU_CPU_TYPE_${ARCH} archs)
 set(QEMU_FLAGS_${ARCH} -cpu archs)
+elseif(${CONFIG_SOC_QEMU_ARC_HS6X})
+set(QEMU_ARCH arc64)
+set(QEMU_CPU_TYPE_${ARCH} arc64)
+set(QEMU_FLAGS_${ARCH} -cpu hs6x)
 endif()
 
+# For old QEMU we had 'simhs' qemu board, however we are going to rename it
+# to 'virt' board. It will be renamed in ARC QEMU in the nearest Zephyr SDK
+# (where ARCv3 HS6x support will be added to QEMU)
+# Let's rely on the QEMU defaults instead of specifying exact board name,
+# until the updated Zephyr SDK will be set as default. By that we keep both SDKs
+# (old and new) working for ARCv2.
+# After that we can specify board explicitly with '-M virt' option.
 list(APPEND QEMU_FLAGS_${ARCH}
-  -M simhs
   -m 8M
   -nographic
   -no-reboot
diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x.dts b/boards/arc/qemu_arc/qemu_arc_hs6x.dts
new file mode 100644
index 0000000000000..751e42ea1ad98
--- /dev/null
+++ b/boards/arc/qemu_arc/qemu_arc_hs6x.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020, Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "qemu_arc.dtsi"
+
+/ {
+	model = "QEMU ARC HS";
+	compatible = "qemu,archs";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,archs";
+			reg = <0>;
+		};
+	};
+};
diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x.yaml b/boards/arc/qemu_arc/qemu_arc_hs6x.yaml
new file mode 100644
index 0000000000000..181f45cffff6c
--- /dev/null
+++ b/boards/arc/qemu_arc/qemu_arc_hs6x.yaml
@@ -0,0 +1,11 @@
+identifier: qemu_arc_hs6x
+name: QEMU Emulation for ARC HS
+type: qemu
+simulation: qemu
+arch: arc
+toolchain:
+  - cross-compile
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x_defconfig b/boards/arc/qemu_arc/qemu_arc_hs6x_defconfig
new file mode 100644
index 0000000000000..a5c5235ff270c
--- /dev/null
+++ b/boards/arc/qemu_arc/qemu_arc_hs6x_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ISA_ARCV3=y
+CONFIG_SOC_QEMU_ARC=y
+CONFIG_SOC_QEMU_ARC_HS6X=y
+CONFIG_XIP=n
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_PRINTK=y
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_ARC_HAS_STACK_CHECKING=n
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_QEMU_ICOUNT_SHIFT=6
diff --git a/cmake/emu/nsim.cmake b/cmake/emu/nsim.cmake
index 25c4121fe2359..9126627481bfd 100644
--- a/cmake/emu/nsim.cmake
+++ b/cmake/emu/nsim.cmake
@@ -35,6 +35,8 @@ elseif(${CONFIG_SOC_NSIM_SEM})
  set(NSIM_PROPS nsim_sem.props)
 elseif(${CONFIG_SOC_NSIM_HS})
  set(NSIM_PROPS nsim_hs.props)
+elseif(${CONFIG_SOC_NSIM_HS6X})
+ set(NSIM_PROPS nsim_hs6x.props)
 endif()
 
 add_custom_target(run
diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake
index e2ff8c0e7427c..2952384ce7358 100644
--- a/cmake/gcc-m-cpu.cmake
+++ b/cmake/gcc-m-cpu.cmake
@@ -54,8 +54,10 @@ elseif("${ARCH}" STREQUAL "arc")
     set(GCC_M_CPU em4_dmips)
   elseif(CONFIG_CPU_EM4_FPUDA)
     set(GCC_M_CPU em4_fpuda)
-  elseif(CONFIG_CPU_ARCHS)
+  elseif(CONFIG_CPU_HS3X)
     set(GCC_M_CPU hs)
+  elseif(CONFIG_CPU_HS6X)
+    set(GCC_M_CPU arc64)
   elseif(CONFIG_CPU_EM4)
     set(GCC_M_CPU arcem)
   elseif(CONFIG_CPU_EM6)
diff --git a/include/arch/arc/arch.h b/include/arch/arc/arch.h
index ee84bb07245e1..d5fa5d7b3e1e8 100644
--- a/include/arch/arc/arch.h
+++ b/include/arch/arc/arch.h
@@ -21,15 +21,18 @@
 #include <arch/common/ffs.h>
 #include <arch/arc/thread.h>
 #include <arch/common/sys_bitops.h>
-#ifdef CONFIG_ISA_ARCV2
+#include "sys-io-common.h"
+
 #include <arch/arc/v2/exc.h>
 #include <arch/arc/v2/irq.h>
-#include <arch/arc/v2/error.h>
 #include <arch/arc/v2/misc.h>
 #include <arch/arc/v2/aux_regs.h>
 #include <arch/arc/v2/arcv2_irq_unit.h>
 #include <arch/arc/v2/asm_inline.h>
 #include <arch/common/addr_types.h>
+#include <arch/arc/v2/error.h>
+
+#ifdef CONFIG_ISA_ARCV2
 #include "v2/sys_io.h"
 #ifdef CONFIG_ARC_CONNECT
 #include <arch/arc/v2/arc_connect.h>
@@ -45,7 +48,11 @@
 extern "C" {
 #endif
 
+#ifdef CONFIG_64BIT
+#define ARCH_STACK_PTR_ALIGN	8
+#else
 #define ARCH_STACK_PTR_ALIGN	4
+#endif /* CONFIG_64BIT */
 
 /* Indicate, for a minimally sized MPU region, how large it must be and what
  * its base address must be aligned to.
diff --git a/include/arch/arc/arch_inlines.h b/include/arch/arc/arch_inlines.h
index c06fd0cb44b16..24483501bb68c 100644
--- a/include/arch/arc/arch_inlines.h
+++ b/include/arch/arc/arch_inlines.h
@@ -12,9 +12,7 @@
 
 #include <kernel_structs.h>
 
-#ifdef CONFIG_ISA_ARCV2
 #include <arch/arc/v2/aux_regs.h>
-#endif
 
 static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
 {
diff --git a/include/arch/arc/asm-compat/asm-macro-32-bit-gnu.h b/include/arch/arc/asm-compat/asm-macro-32-bit-gnu.h
new file mode 100644
index 0000000000000..15f5c7e4aaa7e
--- /dev/null
+++ b/include/arch/arc/asm-compat/asm-macro-32-bit-gnu.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (C) 2021 Synopsys, Inc. (www.synopsys.com)
+ *
+ * Author: Vineet Gupta <vgupta@synopsys.com>
+ *
+ * ALU/Memory instructions pseudo-mnemonics for ARCv2 and ARC32 ISA
+ */
+
+.irp    cc,,.hi,.nz
+.macro MOVR\cc d, s
+	mov\cc \d, \s
+.endm
+.endr
+
+.irp    aa,,.ab,.as,.aw
+.macro LDR\aa d, s, off=0
+	ld\aa  \d, [\s, \off]
+.endm
+.endr
+
+.irp    aa,,.ab,.as,.aw
+.macro STR\aa d, s, off=0
+	; workaround assembler barfing for ST r, [@symb, 0]
+	.if     \off == 0
+		st\aa  \d, [\s]
+	.else
+		st\aa  \d, [\s, \off]
+	.endif
+.endm
+.endr
+
+.macro PUSHR r
+	push \r
+.endm
+
+.macro POPR r
+	pop \r
+.endm
+
+.macro LRR d, aux
+	lr      \d, \aux
+.endm
+
+.macro SRR d, aux
+	sr      \d, \aux
+.endm
+
+.irp    cc,,.nz
+.macro ADDR\cc d, s, v
+	add\cc \d, \s, \v
+.endm
+.endr
+
+.irp    cc,,.nz
+.macro ADD2R\cc d, s, v
+	add2\cc  \d, \s, \v
+.endm
+.endr
+
+.macro ADD3R d, s, v
+	add3	\d, \s, \v
+.endm
+
+.macro SUBR d, s, v
+	sub     \d, \s, \v
+.endm
+
+.macro BMSKNR d, s, v
+	bmskn   \d, \s, \v
+.endm
+
+.macro LSRR d, s, v
+	lsr	\d, \s, \v
+.endm
+
+.macro ASLR d, s, v
+	asl \d, \s, \v
+.endm
+
+.macro ANDR d, s, v
+	and \d, \s, \v
+.endm
+
+.macro ORR, d, s, v
+	or \d, \s, \v
+.endm
+
+.irp    cc,ne,eq
+.macro BRR\cc d, s, lbl
+	br\cc  \d, \s, \lbl
+.endm
+.endr
+
+.macro BREQR d, s, lbl
+	breq \d, \s, \lbl
+.endm
+
+.macro CMPR op1, op2
+	cmp \op1, \op2
+.endm
diff --git a/include/arch/arc/asm-compat/asm-macro-32-bit-mwdt.h b/include/arch/arc/asm-compat/asm-macro-32-bit-mwdt.h
new file mode 100644
index 0000000000000..be4bf6d1b2a8f
--- /dev/null
+++ b/include/arch/arc/asm-compat/asm-macro-32-bit-mwdt.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (C) 2021 Synopsys, Inc. (www.synopsys.com)
+ *
+ * ALU/Memory instructions pseudo-mnemonics for ARCv2 and ARC32 ISA
+ */
+
+.macro MOVR, d, s
+	mov\&$suffix d, s
+.endm
+
+
+.macro LDR, d, s, off
+	.if $narg == 2
+		ld\&$suffix  d, [s]
+	.else
+		ld\&$suffix  d, [s, off]
+	.endif
+.endm
+
+.macro STR, d, s, off
+	.if $narg == 2
+		st\&$suffix  d, [s]
+	.else
+		st\&$suffix  d, [s, off]
+	.endif
+.endm
+
+
+.macro PUSHR, r
+	push r
+.endm
+
+.macro POPR, r
+	pop r
+.endm
+
+.macro LRR, d, aux
+	lr d, aux
+.endm
+
+.macro SRR, d, aux
+	sr d, aux
+.endm
+
+
+.macro ADDR, d, s, v
+	add\&$suffix d, s, v
+.endm
+
+.macro ADD2R, d, s, v
+	add2\&$suffix d, s, v
+.endm
+
+.macro ADD3R, d, s, v
+	add3 d, s, v
+.endm
+
+.macro SUBR, d, s, v
+	sub d, s, v
+.endm
+
+.macro BMSKNR, d, s, v
+	bmskn d, s, v
+.endm
+
+.macro LSRR, d, s, v
+	lsr d, s, v
+.endm
+
+.macro ASLR, d, s, v
+	asl d, s, v
+.endm
+
+.macro ANDR, d, s, v
+	and d, s, v
+.endm
+
+.macro ORR, d, s, v
+	or d, s, v
+.endm
+
+.macro BRR, d, s, lbl
+	br\&$suffix d, s, lbl
+.endm
+
+.macro BREQR, d, s, lbl
+	breq d, s, lbl
+.endm
+
+.macro CMPR, op1, op2
+	cmp op1, op2
+.endm
diff --git a/include/arch/arc/asm-compat/asm-macro-64-bit-gnu.h b/include/arch/arc/asm-compat/asm-macro-64-bit-gnu.h
new file mode 100644
index 0000000000000..ba5d84b5df392
--- /dev/null
+++ b/include/arch/arc/asm-compat/asm-macro-64-bit-gnu.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (C) 2021 Synopsys, Inc. (www.synopsys.com)
+ *
+ * Author: Vineet Gupta <vgupta@synopsys.com>
+ *
+ * pseudo-mnemonics for ALU/Memory instructions for ARC64 ISA
+ */
+
+.irp    cc,,.hi,.nz
+.macro MOVR\cc d, s
+	movl\cc   \d, \s
+.endm
+.endr
+
+.irp    aa,,.ab,.as,.aw
+.macro LDR\aa d, s, off=0
+	ldl\aa \d, [\s, \off]
+.endm
+.endr
+
+.irp    aa,.ab,.as,.aw
+.macro STR\aa d, s, off=0
+	; workaround assembler barfing for ST r, [@symb, 0]
+	.if \off == 0
+		stl\aa \d, [\s]
+	.else
+		stl\aa \d, [\s, \off]
+	.endif
+.endm
+.endr
+
+.macro STR d, s, off=0
+	.if \off == 0
+		stl \d, [\s]
+	.else
+		.if \off > 256
+			STR.as \d, \s, \off / 8
+		.else
+			stl    \d, [\s, \off]
+		.endif
+	.endif
+.endm
+
+.macro PUSHR r
+	pushl   \r
+.endm
+
+.macro POPR r
+	popl    \r
+.endm
+
+.macro LRR d, aux
+	lrl     \d, \aux
+.endm
+
+.macro SRR d, aux
+	srl      \d, \aux
+.endm
+
+.irp    cc,,.nz
+.macro ADDR\cc d, s, v
+	addl\cc  \d, \s, \v
+.endm
+.endr
+
+.irp    cc,,.nz
+.macro ADD2R\cc d, s, v
+	add2l\cc \d, \s, \v
+.endm
+.endr
+
+.macro ADD3R d, s, v
+	add3l \d, \s, \v
+.endm
+
+.macro SUBR d, s, v
+	subl     \d, \s, \v
+.endm
+
+.macro BMSKNR d, s, v
+	bmsknl   \d, \s, \v
+.endm
+
+.macro LSRR d, s, v
+	lsrl	\d, \s, \v
+.endm
+
+.macro ASLR d, s, v
+	asll \d, \s, \v
+.endm
+
+.macro ANDR d, s, v
+	andl \d, \s, \v
+.endm
+
+.macro ORR, d, s, v
+	orl \d, \s, \v
+.endm
+
+.irp    cc,ne,eq
+.macro BRR\cc d, s, lbl
+	br\cc\()l  \d, \s, \lbl
+.endm
+.endr
+
+.macro BREQR d, s, lbl
+	breql \d, \s, \lbl
+.endm
+
+.macro CMPR op1, op2
+	cmpl \op1, \op2
+.endm
diff --git a/include/arch/arc/asm-compat/assembler.h b/include/arch/arc/asm-compat/assembler.h
new file mode 100644
index 0000000000000..62aac896ae673
--- /dev/null
+++ b/include/arch/arc/asm-compat/assembler.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (C) 2021 Synopsys, Inc. (www.synopsys.com)
+ *
+ * Author: Vineet Gupta <vgupta@synopsys.com>
+ *
+ * Top level include file provding ISA pseudo-mnemonics for use in assemmler
+ * and inline assembly.
+ *
+ *  - Helps code reuse across ARC64/ARC32/ARCv2
+ *    e.g. "LDR" maps to 'LD' on 32-bit ISA, 'LDL' on 64-bit ARCv2/ARC64
+ *
+ *  - Provides emulation with multiple instructions if the case be
+ *    e.g. "DBNZ" implemented using 'SUB' and 'BRNE'
+ *
+ *  - Looks more complex than it really is: mainly because Kconfig defines
+ *    are not "honored" in inline assembly. So each varaint is unconditional
+ *    code in a standalone file with Kconfig based #ifdef'ry here. During the
+ *    build process, the "C" preprocessor runs through this file, leaving
+ *    just the final variant include in code fed to compiler/assembler.
+ */
+
+#ifndef __ASM_ARC_ASM_H
+#define __ASM_ARC_ASM_H 1
+
+#ifdef _ASMLANGUAGE
+
+#if defined(CONFIG_ISA_ARCV3) && defined(CONFIG_64BIT)
+#define ARC_PTR		.xword
+#define ARC_REGSZ	8
+#define ARC_REGSHIFT	3
+#include "asm-macro-64-bit-gnu.h"
+#else
+#define ARC_PTR		.word
+#define ARC_REGSZ	4
+#define ARC_REGSHIFT	2
+
+#if defined(__CCAC__)
+#include "asm-macro-32-bit-mwdt.h"
+#else
+#include "asm-macro-32-bit-gnu.h"
+#endif /* defined(__CCAC__) */
+
+#endif
+
+#else	/* !_ASMLANGUAGE */
+
+#error "asm-compat macroses used not in assembler code!"
+
+#endif	/* _ASMLANGUAGE */
+
+#endif
diff --git a/include/arch/arc/sys-io-common.h b/include/arch/arc/sys-io-common.h
new file mode 100644
index 0000000000000..5644c9820a4dc
--- /dev/null
+++ b/include/arch/arc/sys-io-common.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2021 Synopsys.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_ARCH_ARC_SYS_IO_COMMON_H_
+#define ZEPHYR_INCLUDE_ARCH_ARC_SYS_IO_COMMON_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <toolchain.h>
+#include <sys/sys_io.h>
+#include <arch/arc/v2/aux_regs.h>
+
+#include <zephyr/types.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static ALWAYS_INLINE uint8_t sys_read8(mem_addr_t addr)
+{
+	uint8_t value;
+
+	compiler_barrier();
+	value = *(volatile uint8_t *)addr;
+	compiler_barrier();
+
+	return value;
+}
+
+static ALWAYS_INLINE void sys_write8(uint8_t data, mem_addr_t addr)
+{
+	compiler_barrier();
+	*(volatile uint8_t *)addr = data;
+	compiler_barrier();
+}
+
+static ALWAYS_INLINE uint16_t sys_read16(mem_addr_t addr)
+{
+	uint16_t value;
+
+	compiler_barrier();
+	value = *(volatile uint16_t *)addr;
+	compiler_barrier();
+
+	return value;
+}
+
+static ALWAYS_INLINE void sys_write16(uint16_t data, mem_addr_t addr)
+{
+	compiler_barrier();
+	*(volatile uint16_t *)addr = data;
+	compiler_barrier();
+}
+
+static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
+{
+	uint32_t value;
+
+	compiler_barrier();
+	value = *(volatile uint32_t *)addr;
+	compiler_barrier();
+
+	return value;
+}
+
+static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
+{
+	compiler_barrier();
+	*(volatile uint32_t *)addr = data;
+	compiler_barrier();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* ZEPHYR_INCLUDE_ARCH_ARC_SYS_IO_COMMON_H_ */
diff --git a/include/arch/arc/thread.h b/include/arch/arc/thread.h
index af7ab03232523..c1e8203cbf7a4 100644
--- a/include/arch/arc/thread.h
+++ b/include/arch/arc/thread.h
@@ -35,29 +35,29 @@ extern "C" {
 #endif
 
 struct _callee_saved {
-	uint32_t sp; /* r28 */
+	uintptr_t sp; /* r28 */
 };
 typedef struct _callee_saved _callee_saved_t;
 
 struct _thread_arch {
 
 	/* one of the _CAUSE_xxxx definitions above */
-	int relinquish_cause;
+	int32_t relinquish_cause;
 
 #ifdef CONFIG_ARC_STACK_CHECKING
 	/* High address of stack region, stack grows downward from this
 	 * location. Usesd for hardware stack checking
 	 */
-	uint32_t k_stack_base;
-	uint32_t k_stack_top;
+	uintptr_t k_stack_base;
+	uintptr_t k_stack_top;
 #ifdef CONFIG_USERSPACE
-	uint32_t u_stack_base;
-	uint32_t u_stack_top;
+	uintptr_t u_stack_base;
+	uintptr_t u_stack_top;
 #endif
 #endif
 
 #ifdef CONFIG_USERSPACE
-	uint32_t priv_stack_start;
+	uintptr_t priv_stack_start;
 #endif
 };
 
diff --git a/include/arch/arc/v2/sys_io.h b/include/arch/arc/v2/sys_io.h
index 7146feb887f1d..41fb41d5d25e5 100644
--- a/include/arch/arc/v2/sys_io.h
+++ b/include/arch/arc/v2/sys_io.h
@@ -126,60 +126,6 @@ static ALWAYS_INLINE
 	return ret;
 }
 
-static ALWAYS_INLINE uint8_t sys_read8(mem_addr_t addr)
-{
-	uint8_t value;
-
-	compiler_barrier();
-	value = *(volatile uint8_t *)addr;
-	compiler_barrier();
-
-	return value;
-}
-
-static ALWAYS_INLINE void sys_write8(uint8_t data, mem_addr_t addr)
-{
-	compiler_barrier();
-	*(volatile uint8_t *)addr = data;
-	compiler_barrier();
-}
-
-static ALWAYS_INLINE uint16_t sys_read16(mem_addr_t addr)
-{
-	uint16_t value;
-
-	compiler_barrier();
-	value = *(volatile uint16_t *)addr;
-	compiler_barrier();
-
-	return value;
-}
-
-static ALWAYS_INLINE void sys_write16(uint16_t data, mem_addr_t addr)
-{
-	compiler_barrier();
-	*(volatile uint16_t *)addr = data;
-	compiler_barrier();
-}
-
-static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
-{
-	uint32_t value;
-
-	compiler_barrier();
-	value = *(volatile uint32_t *)addr;
-	compiler_barrier();
-
-	return value;
-}
-
-static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
-{
-	compiler_barrier();
-	*(volatile uint32_t *)addr = data;
-	compiler_barrier();
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/linker/linker-tool-gcc.h b/include/linker/linker-tool-gcc.h
index 1ea18ad217fb6..16acaa6b8e52f 100644
--- a/include/linker/linker-tool-gcc.h
+++ b/include/linker/linker-tool-gcc.h
@@ -27,7 +27,11 @@
 #elif defined(CONFIG_ARM64)
 	OUTPUT_FORMAT("elf64-littleaarch64")
 #elif defined(CONFIG_ARC)
-	OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")
+	#if defined(CONFIG_64BIT)
+		OUTPUT_FORMAT("elf64-littlearc")
+	#else
+		OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")
+	#endif
 #elif defined(CONFIG_X86)
 	#if defined(CONFIG_X86_64)
 		OUTPUT_FORMAT("elf64-x86-64")
diff --git a/lib/libc/minimal/include/sys/types.h b/lib/libc/minimal/include/sys/types.h
index 13839c0e3a1ec..ecb06cd67632e 100644
--- a/lib/libc/minimal/include/sys/types.h
+++ b/lib/libc/minimal/include/sys/types.h
@@ -25,7 +25,7 @@ typedef __SIZE_TYPE__ ssize_t;
 #if !defined(__off_t_defined)
 #define __off_t_defined
 
-#if defined(__i386) || defined(__x86_64)
+#if defined(__i386) || defined(__x86_64) || defined(__ARC64__)
 typedef long int off_t; /* "long" works for all of i386, X32 and true 64 bit */
 #elif defined(__ARM_ARCH)
 typedef int off_t;
diff --git a/soc/arc/snps_nsim/CMakeLists.txt b/soc/arc/snps_nsim/CMakeLists.txt
index 5e13cd398a91b..5a82441d0061d 100644
--- a/soc/arc/snps_nsim/CMakeLists.txt
+++ b/soc/arc/snps_nsim/CMakeLists.txt
@@ -2,13 +2,17 @@
 
 if(COMPILER STREQUAL gcc)
   # GNU compiler options
-  zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata)
-  zephyr_compile_options_ifdef(CONFIG_CPU_ARCEM -mmpy-option=wlh1)
-  zephyr_compile_options_ifdef(CONFIG_CPU_ARCHS -mmpy-option=plus_qmacw)
-  if(CONFIG_CPU_ARCHS)
-    zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all)
-  else()
-    zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
+  zephyr_compile_options(-mcpu=${GCC_M_CPU})
+  if(NOT CONFIG_64BIT)
+    # ISA_ARCV2 & 32BIT
+    zephyr_compile_options(-mno-sdata)
+    zephyr_compile_options_ifdef(CONFIG_CPU_ARCEM -mmpy-option=wlh1)
+    zephyr_compile_options_ifdef(CONFIG_CPU_ARCHS -mmpy-option=plus_qmacw)
+    if(CONFIG_CPU_ARCHS)
+      zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all)
+    else()
+      zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
+    endif()
   endif()
 else()
   # MWDT compiler options
diff --git a/soc/arc/snps_nsim/Kconfig b/soc/arc/snps_nsim/Kconfig
index 9c2cd406f3470..72f41b0a002f8 100644
--- a/soc/arc/snps_nsim/Kconfig
+++ b/soc/arc/snps_nsim/Kconfig
@@ -29,4 +29,7 @@ config SOC_NSIM_HS_SMP
 	bool "Multi-core Synopsys ARC HS in nSIM"
 	select CPU_HAS_FPU
 
+config SOC_NSIM_HS6X
+	bool "Synopsys ARC HS6x in nSIM"
+
 endchoice
diff --git a/soc/arc/snps_nsim/Kconfig.defconfig b/soc/arc/snps_nsim/Kconfig.defconfig
index a50ed9d2df4b9..8b7842e3633f9 100644
--- a/soc/arc/snps_nsim/Kconfig.defconfig
+++ b/soc/arc/snps_nsim/Kconfig.defconfig
@@ -17,5 +17,6 @@ source "soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22"
 source "soc/arc/snps_nsim/Kconfig.defconfig.sem"
 source "soc/arc/snps_nsim/Kconfig.defconfig.hs"
 source "soc/arc/snps_nsim/Kconfig.defconfig.hs_smp"
+source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x"
 
 endif # SOC_NSIM
diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs6x b/soc/arc/snps_nsim/Kconfig.defconfig.hs6x
new file mode 100644
index 0000000000000..af92cd694669d
--- /dev/null
+++ b/soc/arc/snps_nsim/Kconfig.defconfig.hs6x
@@ -0,0 +1,26 @@
+# Copyright (c) 2021 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_HS6X
+
+config CPU_HS6X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 50000000
+
+config HARVARD
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+endif # SOC_NSIM_HS6X
diff --git a/soc/arc/snps_qemu/CMakeLists.txt b/soc/arc/snps_qemu/CMakeLists.txt
index 569b18ad152b6..0dbc5b846bb6d 100644
--- a/soc/arc/snps_qemu/CMakeLists.txt
+++ b/soc/arc/snps_qemu/CMakeLists.txt
@@ -1,2 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
-zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata)
+zephyr_compile_options(-mcpu=${GCC_M_CPU})
+
+if(NOT CONFIG_64BIT)
+  zephyr_compile_options(-mno-sdata)
+endif()
diff --git a/soc/arc/snps_qemu/Kconfig b/soc/arc/snps_qemu/Kconfig
index fbfbb431da49b..a8ee136c003f5 100644
--- a/soc/arc/snps_qemu/Kconfig
+++ b/soc/arc/snps_qemu/Kconfig
@@ -12,4 +12,7 @@ config SOC_QEMU_ARC_EM
 config SOC_QEMU_ARC_HS
 	bool "Synopsys ARC HS in QEMU"
 
+config SOC_QEMU_ARC_HS6X
+	bool "Synopsys ARC HS in QEMU"
+
 endchoice
diff --git a/soc/arc/snps_qemu/Kconfig.defconfig b/soc/arc/snps_qemu/Kconfig.defconfig
index ef9386828e106..42eed9085da07 100644
--- a/soc/arc/snps_qemu/Kconfig.defconfig
+++ b/soc/arc/snps_qemu/Kconfig.defconfig
@@ -29,5 +29,6 @@ config NUM_IRQS
 
 source "soc/arc/snps_qemu/Kconfig.defconfig.em"
 source "soc/arc/snps_qemu/Kconfig.defconfig.hs"
+source "soc/arc/snps_qemu/Kconfig.defconfig.hs6x"
 
 endif
diff --git a/soc/arc/snps_qemu/Kconfig.defconfig.hs6x b/soc/arc/snps_qemu/Kconfig.defconfig.hs6x
new file mode 100644
index 0000000000000..1b4d6884ee1f5
--- /dev/null
+++ b/soc/arc/snps_qemu/Kconfig.defconfig.hs6x
@@ -0,0 +1,9 @@
+# Copyright (c) 2021 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_QEMU_ARC_HS6X
+
+config CPU_HS6X
+	default y
+
+endif
diff --git a/tests/kernel/common/testcase.yaml b/tests/kernel/common/testcase.yaml
index 95afb89a43dd4..b21432bce107d 100644
--- a/tests/kernel/common/testcase.yaml
+++ b/tests/kernel/common/testcase.yaml
@@ -23,6 +23,7 @@ tests:
     extra_configs:
       - CONFIG_CBPRINTF_NANO=y
       - CONFIG_CBPRINTF_REDUCED_INTEGRAL=y
+    platform_exclude: qemu_arc_hs6x
   kernel.common.nano64:
     tags: kernel userspace
     min_flash: 33