From 560596fdd1eeafe70a6d17d74979e5eb595c1177 Mon Sep 17 00:00:00 2001 From: Kamil Serwus Date: Sat, 22 Oct 2022 20:46:46 +0200 Subject: [PATCH 1/4] manifest: update hal atmel for c2x support Hal atmel intruduces c20/c21 series support. Signed-off-by: Kamil Serwus --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index f73eee6d92aa6..d5a3f83acff87 100644 --- a/west.yml +++ b/west.yml @@ -52,7 +52,7 @@ manifest: groups: - hal - name: hal_atmel - revision: 43c73d862a78cd5a18a6e24b58cf6980016dbe9e + revision: d45adfb6897aba323cac29cdda8070ce4f23f014 path: modules/hal/atmel groups: - hal From 85116334f32fda199faf2f8a528ecb98c0ead07c Mon Sep 17 00:00:00 2001 From: Kamil Serwus Date: Sun, 23 Oct 2022 21:39:56 +0200 Subject: [PATCH 2/4] soc: arm: atmel: Add revisions to soc Some SAM0 contains revisions with separated includes for example SAMC21 and SAMC21N. Signed-off-by: Kamil Serwus Co-authored-by: Gerson Fernando Budke --- soc/arm/atmel_sam0/Kconfig | 1 + soc/arm/atmel_sam0/Kconfig.soc.revisions | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 soc/arm/atmel_sam0/Kconfig.soc.revisions diff --git a/soc/arm/atmel_sam0/Kconfig b/soc/arm/atmel_sam0/Kconfig index e8e704fee30b7..f59d5639e1f25 100644 --- a/soc/arm/atmel_sam0/Kconfig +++ b/soc/arm/atmel_sam0/Kconfig @@ -17,5 +17,6 @@ source "soc/arm/atmel_sam0/common/Kconfig.saml2x" source "soc/arm/atmel_sam0/common/Kconfig.samd2x" source "soc/arm/atmel_sam0/common/Kconfig.samd5x" source "soc/arm/atmel_sam0/*/Kconfig.soc" +source "soc/arm/atmel_sam0/Kconfig.soc.revisions" endif diff --git a/soc/arm/atmel_sam0/Kconfig.soc.revisions b/soc/arm/atmel_sam0/Kconfig.soc.revisions new file mode 100644 index 0000000000000..a152528ac7b79 --- /dev/null +++ b/soc/arm/atmel_sam0/Kconfig.soc.revisions @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_REVISION_N + bool + +config SOC_SERIES_REVISION + string + default "n" if SOC_SERIES_REVISION_N + default "" From 4bd94f501a24e109844b7013512d0ff363e60b33 Mon Sep 17 00:00:00 2001 From: Kamil Serwus Date: Sun, 23 Oct 2022 12:41:43 +0200 Subject: [PATCH 3/4] soc: atmel: add base support for C2x SOC Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+. C21 contains CAN interface. The init routines are same for SAMC20 and SAMC21. They use one clock OSC48M without configuration. The code is inspirated from atmel_sam0/samd21. Signed-off-by: Kamil Serwus --- drivers/flash/Kconfig.sam0 | 2 + dts/arm/atmel/samc20x15.dtsi | 22 ++ dts/arm/atmel/samc20x16.dtsi | 22 ++ dts/arm/atmel/samc20x17.dtsi | 22 ++ dts/arm/atmel/samc20x18.dtsi | 22 ++ dts/arm/atmel/samc21.dtsi | 47 ++++ dts/arm/atmel/samc21x15.dtsi | 22 ++ dts/arm/atmel/samc21x16.dtsi | 22 ++ dts/arm/atmel/samc21x17.dtsi | 22 ++ dts/arm/atmel/samc21x18.dtsi | 22 ++ dts/arm/atmel/samc2x.dtsi | 230 ++++++++++++++++++ dts/bindings/clock/atmel,samc2x-gclk.yaml | 18 ++ dts/bindings/clock/atmel,samc2x-mclk.yaml | 19 ++ soc/arm/atmel_sam0/Kconfig | 1 + soc/arm/atmel_sam0/common/CMakeLists.txt | 2 + soc/arm/atmel_sam0/common/Kconfig.samc2x | 6 + soc/arm/atmel_sam0/common/soc_samc2x.c | 69 ++++++ .../samc20/Kconfig.defconfig.series | 35 +++ soc/arm/atmel_sam0/samc20/Kconfig.series | 15 ++ soc/arm/atmel_sam0/samc20/Kconfig.soc | 60 +++++ soc/arm/atmel_sam0/samc20/linker.ld | 8 + soc/arm/atmel_sam0/samc20/soc.h | 67 +++++ .../samc21/Kconfig.defconfig.series | 35 +++ soc/arm/atmel_sam0/samc21/Kconfig.series | 15 ++ soc/arm/atmel_sam0/samc21/Kconfig.soc | 60 +++++ soc/arm/atmel_sam0/samc21/linker.ld | 8 + soc/arm/atmel_sam0/samc21/soc.h | 67 +++++ 27 files changed, 940 insertions(+) create mode 100644 dts/arm/atmel/samc20x15.dtsi create mode 100644 dts/arm/atmel/samc20x16.dtsi create mode 100644 dts/arm/atmel/samc20x17.dtsi create mode 100644 dts/arm/atmel/samc20x18.dtsi create mode 100644 dts/arm/atmel/samc21.dtsi create mode 100644 dts/arm/atmel/samc21x15.dtsi create mode 100644 dts/arm/atmel/samc21x16.dtsi create mode 100644 dts/arm/atmel/samc21x17.dtsi create mode 100644 dts/arm/atmel/samc21x18.dtsi create mode 100644 dts/arm/atmel/samc2x.dtsi create mode 100644 dts/bindings/clock/atmel,samc2x-gclk.yaml create mode 100644 dts/bindings/clock/atmel,samc2x-mclk.yaml create mode 100644 soc/arm/atmel_sam0/common/Kconfig.samc2x create mode 100644 soc/arm/atmel_sam0/common/soc_samc2x.c create mode 100644 soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series create mode 100644 soc/arm/atmel_sam0/samc20/Kconfig.series create mode 100644 soc/arm/atmel_sam0/samc20/Kconfig.soc create mode 100644 soc/arm/atmel_sam0/samc20/linker.ld create mode 100644 soc/arm/atmel_sam0/samc20/soc.h create mode 100644 soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series create mode 100644 soc/arm/atmel_sam0/samc21/Kconfig.series create mode 100644 soc/arm/atmel_sam0/samc21/Kconfig.soc create mode 100644 soc/arm/atmel_sam0/samc21/linker.ld create mode 100644 soc/arm/atmel_sam0/samc21/soc.h diff --git a/drivers/flash/Kconfig.sam0 b/drivers/flash/Kconfig.sam0 index e604b0ce8e7c2..accaa30d3039d 100644 --- a/drivers/flash/Kconfig.sam0 +++ b/drivers/flash/Kconfig.sam0 @@ -16,6 +16,8 @@ menuconfig SOC_FLASH_SAM0 config SOC_FLASH_SAM0_EMULATE_BYTE_PAGES bool "Emulate byte-sized pages" depends on SOC_FLASH_SAM0 + default y if SOC_SERIES_SAMC20 || \ + SOC_SERIES_SAMC21 help Emulate a device with byte-sized pages by doing a read/modify/erase/write. diff --git a/dts/arm/atmel/samc20x15.dtsi b/dts/arm/atmel/samc20x15.dtsi new file mode 100644 index 0000000000000..fc1b141dab221 --- /dev/null +++ b/dts/arm/atmel/samc20x15.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(4)>; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(32)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samc20x16.dtsi b/dts/arm/atmel/samc20x16.dtsi new file mode 100644 index 0000000000000..8bffaf7207857 --- /dev/null +++ b/dts/arm/atmel/samc20x16.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(8)>; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(64)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samc20x17.dtsi b/dts/arm/atmel/samc20x17.dtsi new file mode 100644 index 0000000000000..2149e2b589890 --- /dev/null +++ b/dts/arm/atmel/samc20x17.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(16)>; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(128)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samc20x18.dtsi b/dts/arm/atmel/samc20x18.dtsi new file mode 100644 index 0000000000000..d819ae2492ec8 --- /dev/null +++ b/dts/arm/atmel/samc20x18.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(32)>; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(256)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samc21.dtsi b/dts/arm/atmel/samc21.dtsi new file mode 100644 index 0000000000000..f7874487d0dc2 --- /dev/null +++ b/dts/arm/atmel/samc21.dtsi @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * + * SPDX-License-Identifier: Apache-2.0 + */ + + #include + +/ { + aliases { + sercom-4 = &sercom4; + sercom-5 = &sercom5; + }; + + soc { + adc1: adc@42004800 { + compatible = "atmel,sam0-adc"; + status = "disabled"; + reg = <0x42004800 0x30>; + interrupts = <26 0>; + interrupt-names = "resrdy"; + clocks = <&gclk 34>, <&mclk 0x1c 18>; + clock-names = "GCLK", "MCLK"; + gclk = <0>; + prescaler = <4>; + #io-channel-cells = <1>; + }; + + sercom4: sercom@42001400 { + compatible = "atmel,sam0-sercom"; + reg = <0x42001400 0x40>; + interrupts = <13 0>; + clocks = <&gclk 23>, <&mclk 0x1c 5>; + clock-names = "GCLK", "MCLK"; + status = "disabled"; + }; + + sercom5: sercom@42001800 { + compatible = "atmel,sam0-sercom"; + reg = <0x42001800 0x40>; + interrupts = <14 0>; + clocks = <&gclk 25>, <&mclk 0x1c 6>; + clock-names = "GCLK", "MCLK"; + status = "disabled"; + }; + }; +}; diff --git a/dts/arm/atmel/samc21x15.dtsi b/dts/arm/atmel/samc21x15.dtsi new file mode 100644 index 0000000000000..0e4ef46642859 --- /dev/null +++ b/dts/arm/atmel/samc21x15.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(4)>; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(32)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samc21x16.dtsi b/dts/arm/atmel/samc21x16.dtsi new file mode 100644 index 0000000000000..7f66c19dbb306 --- /dev/null +++ b/dts/arm/atmel/samc21x16.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(8)>; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(64)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samc21x17.dtsi b/dts/arm/atmel/samc21x17.dtsi new file mode 100644 index 0000000000000..b09568beb1b5c --- /dev/null +++ b/dts/arm/atmel/samc21x17.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(16)>; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(128)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samc21x18.dtsi b/dts/arm/atmel/samc21x18.dtsi new file mode 100644 index 0000000000000..353c2d23253c2 --- /dev/null +++ b/dts/arm/atmel/samc21x18.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(32)>; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(256)>; + }; + }; + }; +}; diff --git a/dts/arm/atmel/samc2x.dtsi b/dts/arm/atmel/samc2x.dtsi new file mode 100644 index 0000000000000..b6e84c9e464a9 --- /dev/null +++ b/dts/arm/atmel/samc2x.dtsi @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + aliases { + watchdog0 = &wdog; + }; + + chosen { + zephyr,flash-controller = &nvmctrl; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m0+"; + reg = <0>; + }; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + id: device_id@80a00c { + compatible = "atmel,sam0-id"; + reg = <0x0080A00C 0x4>, + <0x0080A040 0x4>, + <0x0080A044 0x4>, + <0x0080A048 0x4>; + }; + + aliases { + port-a = &porta; + port-b = &portb; + port-c = &portc; + + sercom-0 = &sercom0; + sercom-1 = &sercom1; + sercom-2 = &sercom2; + sercom-3 = &sercom3; + + tcc-0 = &tcc0; + tcc-1 = &tcc1; + tcc-2 = &tcc2; + }; + + soc { + nvmctrl: nvmctrl@41004000 { + compatible = "atmel,sam0-nvmctrl"; + reg = <0x41004000 0x22>; + interrupts = <6 0>; + lock-regions = <16>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + write-block-size = <4>; + }; + }; + + mclk: mclk@40000800 { + compatible = "atmel,samc2x-mclk"; + reg = <0x40000800 0x400>; + #clock-cells = <2>; + }; + + gclk: gclk@40001c00 { + compatible = "atmel,samc2x-gclk"; + reg = <0x40001c00 0x400>; + #clock-cells = <1>; + }; + + eic: eic@40002800 { + compatible = "atmel,sam0-eic"; + reg = <0x40002800 0x1C>; + interrupts = <3 0>; + }; + + pinmux_a: pinmux@41000000 { + compatible = "atmel,sam0-pinmux"; + reg = <0x41000000 0x80>; + }; + + wdog: watchdog@40002000 { + compatible = "atmel,sam0-watchdog"; + reg = <0x40002000 9>; + interrupts = <1 0>; + }; + + adc0: adc@42004400 { + compatible = "atmel,sam0-adc"; + status = "disabled"; + reg = <0x42004400 0x30>; + interrupts = <25 0>; + interrupt-names = "resrdy"; + clocks = <&gclk 33>, <&mclk 0x1c 17>; + clock-names = "GCLK", "MCLK"; + gclk = <0>; + prescaler = <4>; + #io-channel-cells = <1>; + }; + + sercom0: sercom@42000400 { + compatible = "atmel,sam0-sercom"; + reg = <0x42000400 0x40>; + interrupts = <9 0>; + clocks = <&gclk 19>, <&mclk 0x1c 1>; + clock-names = "GCLK", "MCLK"; + status = "disabled"; + }; + + sercom1: sercom@42000800 { + compatible = "atmel,sam0-sercom"; + reg = <0x42000800 0x40>; + interrupts = <10 0>; + clocks = <&gclk 20>, <&mclk 0x1c 2>; + clock-names = "GCLK", "MCLK"; + status = "disabled"; + }; + + sercom2: sercom@42000c00 { + compatible = "atmel,sam0-sercom"; + reg = <0x42000c00 0x40>; + interrupts = <11 0>; + clocks = <&gclk 21>, <&mclk 0x1c 3>; + clock-names = "GCLK", "MCLK"; + status = "disabled"; + }; + + sercom3: sercom@42001000 { + compatible = "atmel,sam0-sercom"; + reg = <0x42001000 0x40>; + interrupts = <12 0>; + clocks = <&gclk 22>, <&mclk 0x1c 4>; + clock-names = "GCLK", "MCLK"; + status = "disabled"; + }; + + tcc0: tcc@42002400 { + compatible = "atmel,sam0-tcc"; + reg = <0x42002400 0x80>; + interrupts = <17 0>; + clocks = <&gclk 28>, <&mclk 0x1c 9>; + clock-names = "GCLK", "MCLK"; + + channels = <4>; + counter-size = <24>; + }; + + tcc1: tcc@42002800 { + compatible = "atmel,sam0-tcc"; + reg = <0x42002800 0x80>; + interrupts = <18 0>; + clocks = <&gclk 28>, <&mclk 0x1c 10>; + clock-names = "GCLK", "MCLK"; + + channels = <4>; + counter-size = <24>; + }; + + tcc2: tcc@42002c00 { + compatible = "atmel,sam0-tcc"; + reg = <0x42002c00 0x80>; + interrupts = <19 0>; + clocks = <&gclk 29>, <&mclk 0x1c 11>; + clock-names = "GCLK", "MCLK"; + + channels = <2>; + counter-size = <16>; + }; + + pinctrl: pinctrl@41000000 { + compatible = "atmel,sam0-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x41000000 0x180>; + + porta: gpio@41000000 { + compatible = "atmel,sam0-gpio"; + reg = <0x41000000 0x80>; + gpio-controller; + #gpio-cells = <2>; + #atmel,pin-cells = <2>; + }; + + portb: gpio@41000080 { + compatible = "atmel,sam0-gpio"; + reg = <0x41000080 0x80>; + gpio-controller; + #gpio-cells = <2>; + #atmel,pin-cells = <2>; + }; + + portc: gpio@41000100 { + compatible = "atmel,sam0-gpio"; + reg = <0x41000100 0x80>; + gpio-controller; + #gpio-cells = <2>; + #atmel,pin-cells = <2>; + }; + }; + + rtc: rtc@40002400 { + compatible = "atmel,sam0-rtc"; + reg = <0x40002400 0x1C>; + interrupts = <3 0>; + clock-generator = <0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/dts/bindings/clock/atmel,samc2x-gclk.yaml b/dts/bindings/clock/atmel,samc2x-gclk.yaml new file mode 100644 index 0000000000000..95ef0638d1e4a --- /dev/null +++ b/dts/bindings/clock/atmel,samc2x-gclk.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +description: Atmel SAMC2x Generic Clock Controller (GCLK) + +compatible: "atmel,samc2x-gclk" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 1 + +clock-cells: + - periph_ch diff --git a/dts/bindings/clock/atmel,samc2x-mclk.yaml b/dts/bindings/clock/atmel,samc2x-mclk.yaml new file mode 100644 index 0000000000000..e3a8b0b696b90 --- /dev/null +++ b/dts/bindings/clock/atmel,samc2x-mclk.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2022, Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +description: Atmel SAMC2x Generic Clock Controller (MCLK) + +compatible: "atmel,samc2x-mclk" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 2 + +clock-cells: + - offset + - bit diff --git a/soc/arm/atmel_sam0/Kconfig b/soc/arm/atmel_sam0/Kconfig index f59d5639e1f25..a11cf9b95a960 100644 --- a/soc/arm/atmel_sam0/Kconfig +++ b/soc/arm/atmel_sam0/Kconfig @@ -13,6 +13,7 @@ config SOC_FAMILY string default "atmel_sam0" +source "soc/arm/atmel_sam0/common/Kconfig.samc2x" source "soc/arm/atmel_sam0/common/Kconfig.saml2x" source "soc/arm/atmel_sam0/common/Kconfig.samd2x" source "soc/arm/atmel_sam0/common/Kconfig.samd5x" diff --git a/soc/arm/atmel_sam0/common/CMakeLists.txt b/soc/arm/atmel_sam0/common/CMakeLists.txt index 4c2583792b1d3..7674095e5b18a 100644 --- a/soc/arm/atmel_sam0/common/CMakeLists.txt +++ b/soc/arm/atmel_sam0/common/CMakeLists.txt @@ -7,6 +7,8 @@ zephyr_sources(soc_port.c) zephyr_sources_ifdef(CONFIG_BOOTLOADER_BOSSA bossa.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMC20 soc_samc2x.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMC21 soc_samc2x.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD20 soc_samd2x.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD21 soc_samd2x.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR21 soc_samd2x.c) diff --git a/soc/arm/atmel_sam0/common/Kconfig.samc2x b/soc/arm/atmel_sam0/common/Kconfig.samc2x new file mode 100644 index 0000000000000..3fca87f23ce1d --- /dev/null +++ b/soc/arm/atmel_sam0/common/Kconfig.samc2x @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMC20 || SOC_SERIES_SAMC21 + +endif diff --git a/soc/arm/atmel_sam0/common/soc_samc2x.c b/soc/arm/atmel_sam0/common/soc_samc2x.c new file mode 100644 index 0000000000000..3efc4071eea85 --- /dev/null +++ b/soc/arm/atmel_sam0/common/soc_samc2x.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Atmel SAMC MCU series initialization code + */ + +#include +#include +#include +#include +#include + +static void flash_waitstates_init(void) +{ + /* One wait state at 48 MHz. */ + NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val; +} + +static void osc48m_init(void) +{ + /* Turn off the prescaler */ + OSCCTRL->OSC48MDIV.bit.DIV = 0; + while (OSCCTRL->OSC48MSYNCBUSY.bit.OSC48MDIV) { + } + while (!OSCCTRL->STATUS.bit.OSC48MRDY) { + } +} + +static void mclk_init(void) +{ + MCLK->CPUDIV.reg = MCLK_CPUDIV_CPUDIV_DIV1_Val; +} + +static void gclks_init(void) +{ + GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M) + | GCLK_GENCTRL_DIV(1) + | GCLK_GENCTRL_GENEN; +} + +static int atmel_samc_init(const struct device *arg) +{ + uint32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + flash_waitstates_init(); + osc48m_init(); + mclk_init(); + gclks_init(); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + return 0; +} + +SYS_INIT(atmel_samc_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series new file mode 100644 index 0000000000000..05a52d3af2a61 --- /dev/null +++ b/soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series @@ -0,0 +1,35 @@ +# Atmel SAMC MCU series configuration options + +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMC20 + +config SOC_SERIES + default "samc20" + +config SOC_PART_NUMBER + default "samc20e15a" if SOC_PART_NUMBER_SAMC20E15A + default "samc20e16a" if SOC_PART_NUMBER_SAMC20E16A + default "samc20e17a" if SOC_PART_NUMBER_SAMC20E17A + default "samc20e18a" if SOC_PART_NUMBER_SAMC20E18A + default "samc20g15a" if SOC_PART_NUMBER_SAMC20G15A + default "samc20g16a" if SOC_PART_NUMBER_SAMC20G16A + default "samc20g17a" if SOC_PART_NUMBER_SAMC20G17A + default "samc20g18a" if SOC_PART_NUMBER_SAMC20G18A + default "samc20j15a" if SOC_PART_NUMBER_SAMC20J15A + default "samc20j16a" if SOC_PART_NUMBER_SAMC20J16A + default "samc20j17a" if SOC_PART_NUMBER_SAMC20J17A + default "samc20j17au" if SOC_PART_NUMBER_SAMC20J17AU + default "samc20j18a" if SOC_PART_NUMBER_SAMC20J18A + default "samc20j18au" if SOC_PART_NUMBER_SAMC20J18AU + default "samc20n17a" if SOC_PART_NUMBER_SAMC20N17A + default "samc20n18a" if SOC_PART_NUMBER_SAMC20N18A + +config NUM_IRQS + default 32 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif # SOC_SERIES_SAMC20 diff --git a/soc/arm/atmel_sam0/samc20/Kconfig.series b/soc/arm/atmel_sam0/samc20/Kconfig.series new file mode 100644 index 0000000000000..961ca09955420 --- /dev/null +++ b/soc/arm/atmel_sam0/samc20/Kconfig.series @@ -0,0 +1,15 @@ +# Atmel SAMC20 MCU series + +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC20 + bool "Atmel SAMC20 MCU" + select ARM + select CPU_CORTEX_M0PLUS + select SOC_FAMILY_SAM0 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select ASF + help + Enable support for Atmel SAMC20 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samc20/Kconfig.soc b/soc/arm/atmel_sam0/samc20/Kconfig.soc new file mode 100644 index 0000000000000..9ccd4ca271487 --- /dev/null +++ b/soc/arm/atmel_sam0/samc20/Kconfig.soc @@ -0,0 +1,60 @@ +# Atmel SAMC MCU series + +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Atmel SAMC20 MCU Selection" + depends on SOC_SERIES_SAMC20 + +config SOC_PART_NUMBER_SAMC20E15A + bool "SAMC20E15A" + +config SOC_PART_NUMBER_SAMC20E16A + bool "SAMC20E16A" + +config SOC_PART_NUMBER_SAMC20E17A + bool "SAMC20E17A" + +config SOC_PART_NUMBER_SAMC20E18A + bool "SAMC20E18A" + +config SOC_PART_NUMBER_SAMC20G15A + bool "SAMC20G15A" + +config SOC_PART_NUMBER_SAMC20G16A + bool "SAMC20G16A" + +config SOC_PART_NUMBER_SAMC20G17A + bool "SAMC20G17A" + +config SOC_PART_NUMBER_SAMC20G18A + bool "SAMC20G18A" + +config SOC_PART_NUMBER_SAMC20J15A + bool "SAMC20J15A" + +config SOC_PART_NUMBER_SAMC20J16A + bool "SAMC20J16A" + +config SOC_PART_NUMBER_SAMC20J17A + bool "SAMC20J17A" + +config SOC_PART_NUMBER_SAMC20J17AU + bool "SAMC20J17AU" + +config SOC_PART_NUMBER_SAMC20J18A + bool "SAMC20J18A" + +config SOC_PART_NUMBER_SAMC20J18AU + bool "SAMC20J18AU" + +config SOC_PART_NUMBER_SAMC20N17A + bool "SAMC20N17A" + select SOC_SERIES_REVISION_N + +config SOC_PART_NUMBER_SAMC20N18A + bool "SAMC20N18A" + select SOC_SERIES_REVISION_N + +endchoice diff --git a/soc/arm/atmel_sam0/samc20/linker.ld b/soc/arm/atmel_sam0/samc20/linker.ld new file mode 100644 index 0000000000000..3ff98161e1115 --- /dev/null +++ b/soc/arm/atmel_sam0/samc20/linker.ld @@ -0,0 +1,8 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2017 Google LLC. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/atmel_sam0/samc20/soc.h b/soc/arm/atmel_sam0/samc20/soc.h new file mode 100644 index 0000000000000..cca05ab6521ad --- /dev/null +++ b/soc/arm/atmel_sam0/samc20/soc.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ATMEL_SAMC_SOC_H_ +#define _ATMEL_SAMC_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + + +#if defined(CONFIG_SOC_PART_NUMBER_SAMC20E15A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E16A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E17A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E18A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G15A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G16A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G17A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G18A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J15A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J16A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J17A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J17AU) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J18A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J18AU) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20N17A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20N18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _ATMEL_SAMD51_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series new file mode 100644 index 0000000000000..bc1c4431737f4 --- /dev/null +++ b/soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series @@ -0,0 +1,35 @@ +# Atmel SAMC MCU series configuration options + +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMC21 + +config SOC_SERIES + default "samc21" + +config SOC_PART_NUMBER + default "samc21e15a" if SOC_PART_NUMBER_SAMC21E15A + default "samc21e16a" if SOC_PART_NUMBER_SAMC21E16A + default "samc21e17a" if SOC_PART_NUMBER_SAMC21E17A + default "samc21e18a" if SOC_PART_NUMBER_SAMC21E18A + default "samc21g15a" if SOC_PART_NUMBER_SAMC21G15A + default "samc21g16a" if SOC_PART_NUMBER_SAMC21G16A + default "samc21g17a" if SOC_PART_NUMBER_SAMC21G17A + default "samc21g18a" if SOC_PART_NUMBER_SAMC21G18A + default "samc21j15a" if SOC_PART_NUMBER_SAMC21J15A + default "samc21j16a" if SOC_PART_NUMBER_SAMC21J16A + default "samc21j17a" if SOC_PART_NUMBER_SAMC21J17A + default "samc21j17au" if SOC_PART_NUMBER_SAMC21J17AU + default "samc21j18a" if SOC_PART_NUMBER_SAMC21J18A + default "samc21j18au" if SOC_PART_NUMBER_SAMC21J18AU + default "samc21n17a" if SOC_PART_NUMBER_SAMC21N17A + default "samc21n18a" if SOC_PART_NUMBER_SAMC21N18A + +config NUM_IRQS + default 32 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif # SOC_SERIES_SAMC21 diff --git a/soc/arm/atmel_sam0/samc21/Kconfig.series b/soc/arm/atmel_sam0/samc21/Kconfig.series new file mode 100644 index 0000000000000..3ed3fd2316db5 --- /dev/null +++ b/soc/arm/atmel_sam0/samc21/Kconfig.series @@ -0,0 +1,15 @@ +# Atmel SAMC21 MCU series + +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC21 + bool "Atmel SAMC21 MCU" + select ARM + select CPU_CORTEX_M0PLUS + select SOC_FAMILY_SAM0 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select ASF + help + Enable support for Atmel SAMC21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samc21/Kconfig.soc b/soc/arm/atmel_sam0/samc21/Kconfig.soc new file mode 100644 index 0000000000000..f3f324abf6c9e --- /dev/null +++ b/soc/arm/atmel_sam0/samc21/Kconfig.soc @@ -0,0 +1,60 @@ +# Atmel SAMC MCU series + +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Atmel SAMC21 MCU Selection" + depends on SOC_SERIES_SAMC21 + +config SOC_PART_NUMBER_SAMC21E15A + bool "SAMC21E15A" + +config SOC_PART_NUMBER_SAMC21E16A + bool "SAMC21E16A" + +config SOC_PART_NUMBER_SAMC21E17A + bool "SAMC21E17A" + +config SOC_PART_NUMBER_SAMC21E18A + bool "SAMC21E18A" + +config SOC_PART_NUMBER_SAMC21G15A + bool "SAMC21G15A" + +config SOC_PART_NUMBER_SAMC21G16A + bool "SAMC21G16A" + +config SOC_PART_NUMBER_SAMC21G17A + bool "SAMC21G17A" + +config SOC_PART_NUMBER_SAMC21G18A + bool "SAMC21G18A" + +config SOC_PART_NUMBER_SAMC21J15A + bool "SAMC21J15A" + +config SOC_PART_NUMBER_SAMC21J16A + bool "SAMC21J16A" + +config SOC_PART_NUMBER_SAMC21J17A + bool "SAMC21J17A" + +config SOC_PART_NUMBER_SAMC21J17AU + bool "SAMC21J17AU" + +config SOC_PART_NUMBER_SAMC21J18A + bool "SAMC21J18A" + +config SOC_PART_NUMBER_SAMC21J18AU + bool "SAMC21J18AU" + +config SOC_PART_NUMBER_SAMC21N17A + bool "SAMC21N17A" + select SOC_SERIES_REVISION_N + +config SOC_PART_NUMBER_SAMC21N18A + bool "SAMC21N18A" + select SOC_SERIES_REVISION_N + +endchoice diff --git a/soc/arm/atmel_sam0/samc21/linker.ld b/soc/arm/atmel_sam0/samc21/linker.ld new file mode 100644 index 0000000000000..3ff98161e1115 --- /dev/null +++ b/soc/arm/atmel_sam0/samc21/linker.ld @@ -0,0 +1,8 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2017 Google LLC. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/atmel_sam0/samc21/soc.h b/soc/arm/atmel_sam0/samc21/soc.h new file mode 100644 index 0000000000000..3f258b2eace7b --- /dev/null +++ b/soc/arm/atmel_sam0/samc21/soc.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ATMEL_SAMC_SOC_H_ +#define _ATMEL_SAMC_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + + +#if defined(CONFIG_SOC_PART_NUMBER_SAMC21E15A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E16A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E17A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E18A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G15A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G16A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G17A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G18A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J15A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J16A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J17A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J17AU) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J18A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J18AU) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21N17A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21N18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _ATMEL_SAMD51_SOC_H_ */ From 3eabb38397b8a3496879e5cfadd32bd3a496595e Mon Sep 17 00:00:00 2001 From: Kamil Serwus Date: Sun, 23 Oct 2022 12:59:07 +0200 Subject: [PATCH 4/4] board: samc21: add support for SAMC21N Xplained Pro Board Add basic support board with SAMC21N soc including SPI, UART, I2C, ADC, Flash, Leds. Signed-off-by: Kamil Serwus --- boards/arm/atsamc21n_xpro/Kconfig.board | 8 + boards/arm/atsamc21n_xpro/Kconfig.defconfig | 8 + .../atsamc21n_xpro-pinctrl.dtsi | 64 ++++++ boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts | 153 ++++++++++++++ boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml | 18 ++ .../atsamc21n_xpro/atsamc21n_xpro_defconfig | 11 ++ boards/arm/atsamc21n_xpro/board.cmake | 4 + .../atsamc21n_xpro/doc/img/atsamc21n_xpro.jpg | Bin 0 -> 29697 bytes boards/arm/atsamc21n_xpro/doc/index.rst | 187 ++++++++++++++++++ boards/arm/atsamc21n_xpro/pre_dt_board.cmake | 7 + boards/arm/atsamc21n_xpro/support/openocd.cfg | 25 +++ .../drivers/adc/boards/atsamc21n_xpro.overlay | 28 +++ 12 files changed, 513 insertions(+) create mode 100644 boards/arm/atsamc21n_xpro/Kconfig.board create mode 100644 boards/arm/atsamc21n_xpro/Kconfig.defconfig create mode 100644 boards/arm/atsamc21n_xpro/atsamc21n_xpro-pinctrl.dtsi create mode 100644 boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts create mode 100644 boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml create mode 100644 boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig create mode 100644 boards/arm/atsamc21n_xpro/board.cmake create mode 100644 boards/arm/atsamc21n_xpro/doc/img/atsamc21n_xpro.jpg create mode 100644 boards/arm/atsamc21n_xpro/doc/index.rst create mode 100644 boards/arm/atsamc21n_xpro/pre_dt_board.cmake create mode 100644 boards/arm/atsamc21n_xpro/support/openocd.cfg create mode 100644 samples/drivers/adc/boards/atsamc21n_xpro.overlay diff --git a/boards/arm/atsamc21n_xpro/Kconfig.board b/boards/arm/atsamc21n_xpro/Kconfig.board new file mode 100644 index 0000000000000..ee0ee41e596db --- /dev/null +++ b/boards/arm/atsamc21n_xpro/Kconfig.board @@ -0,0 +1,8 @@ +# SAM C21N Xplained Pro Board configuration + +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ATSAMC21N_XPRO + bool "SAM C21N Xplained Pro" + depends on SOC_PART_NUMBER_SAMC21N18A diff --git a/boards/arm/atsamc21n_xpro/Kconfig.defconfig b/boards/arm/atsamc21n_xpro/Kconfig.defconfig new file mode 100644 index 0000000000000..8827f5c67a826 --- /dev/null +++ b/boards/arm/atsamc21n_xpro/Kconfig.defconfig @@ -0,0 +1,8 @@ +# SAM C21N Xplained Pro board configuration + +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "atsamc21n_xpro" + depends on BOARD_ATSAMC21N_XPRO diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro-pinctrl.dtsi b/boards/arm/atsamc21n_xpro/atsamc21n_xpro-pinctrl.dtsi new file mode 100644 index 0000000000000..735b1b0ddd450 --- /dev/null +++ b/boards/arm/atsamc21n_xpro/atsamc21n_xpro-pinctrl.dtsi @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + + pwm_default: pwm_default { + group1 { + pinmux = ; + }; + }; + + adc0_default: adc0_default { + group1 { + pinmux = ; + }; + }; + + adc1_default: adc1_default { + group1 { + pinmux = ; + }; + }; + + sercom0_uart_default: sercom0_uart_default { + group1 { + pinmux = , + ; + }; + }; + + sercom1_i2c_default: sercom1_i2c_default { + group1 { + pinmux = , + ; + }; + }; + + sercom2_uart_default: sercom1_uart_default { + group1 { + pinmux = , + ; + }; + }; + + sercom4_uart_default: sercom4_uart_default { + group1 { + pinmux = , + ; + }; + }; + + sercom5_spi_default: sercom5_spi_default { + group1 { + pinmux = , + , + ; + }; + }; + +}; diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts b/boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts new file mode 100644 index 0000000000000..14d0dd22d5fbe --- /dev/null +++ b/boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "atsamc21n_xpro-pinctrl.dtsi" + +/ { + model = "SAM C21N Xplained Pro"; + compatible = "atsamc21n,xpro", "atmel,samc21n18a", "atmel,samc21"; + + chosen { + zephyr,console = &sercom4; + zephyr,shell-uart = &sercom4; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + i2c-0 = &sercom1; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portc 05 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc2 1 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&portb 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "User Button"; + }; + }; + +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&adc1 { + pinctrl-0 = <&adc1_default>; + pinctrl-names = "default"; +}; + +&tcc2 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + prescaler = <256>; + #pwm-cells = <2>; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <9600>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom0_uart_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom1_i2c_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom2_uart_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <1>; + + pinctrl-0 = <&sercom4_uart_default>; + pinctrl-names = "default"; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_spi_default>; + pinctrl-names = "default"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@3c000 { + label = "storage"; + reg = <0x0003c000 0x00004000>; + }; + }; +}; diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml b/boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml new file mode 100644 index 0000000000000..f9102d4c560ca --- /dev/null +++ b/boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 +identifier: atsamc21n_xpro +name: SAM C21N Xplained Pro +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - gpio + - i2c + - pwm + - spi diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig b/boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig new file mode 100644 index 0000000000000..7205b28aaad51 --- /dev/null +++ b/boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 +CONFIG_SOC_SERIES_SAMC21=y +CONFIG_SOC_PART_NUMBER_SAMC21N18A=y +CONFIG_BOARD_ATSAMC21N_XPRO=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y diff --git a/boards/arm/atsamc21n_xpro/board.cmake b/boards/arm/atsamc21n_xpro/board.cmake new file mode 100644 index 0000000000000..e181152fed66d --- /dev/null +++ b/boards/arm/atsamc21n_xpro/board.cmake @@ -0,0 +1,4 @@ +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/atsamc21n_xpro/doc/img/atsamc21n_xpro.jpg b/boards/arm/atsamc21n_xpro/doc/img/atsamc21n_xpro.jpg new file mode 100644 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0 HcmV?d00001 diff --git a/boards/arm/atsamc21n_xpro/doc/index.rst b/boards/arm/atsamc21n_xpro/doc/index.rst new file mode 100644 index 0000000000000..07d12d6299e62 --- /dev/null +++ b/boards/arm/atsamc21n_xpro/doc/index.rst @@ -0,0 +1,187 @@ +.. _atsamc21n_xpro: + +SAM C21N Xplained Pro Evaluation Kit +#################################### + +Overview +******** + +The SAM C21N Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM C21N Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. image:: img/atsamc21n_xpro.jpg + :align: center + :alt: ATSAMC21N-XPRO + +Hardware +******** + +- ATSAMC21N18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory, 32 KiB of RAM, 8KB RRW flash +- One yellow user LED +- One mechanical user push button +- One reset button +- One QTouch® button +- On-board USB based EDBG unit with serial console +- Two CAN transceivers + +Supported Features +================== + +The atsamc21n_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - ADC + - on-chip + - Analog to Digital Converter + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +``boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig``. + +Pin Mapping +=========== + +The SAM C21N Xplained Pro evaluation kit has 4 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For mode details please refer to `SAM C21 Family Datasheet`_ and the `SAM C21N +Xplained Pro Schematic`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- ADC0 : PB09 +- ADC1 : PA08 +- SERCOM0 USART TX : PB24 +- SERCOM0 USART RX : PB25 +- SERCOM1 I2C SDA : PA16 +- SERCOM1 I2C SCL : PA17 +- SERCOM2 USART TX : PA12 +- SERCOM2 USART RX : PA13 +- SERCOM4 USART TX : PB10 +- SERCOM4 USART RX : PB11 +- SERCOM5 SPI MISO : PB00 +- SERCOM5 SPI MOSI : PB02 +- SERCOM5 SPI SCK : PB01 +- GPIO/PWM LED0 : PC05 + +System Clock +============ + +The SAMC21 MCU is configured to use the 32.768 kHz internal oscillator +with the on-chip internal oscillator generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMC21 MCU has eight SERCOM based USARTs with three configured as USARTs in +this BSP. SERCOM4 is the default Zephyr console. + +- SERCOM0 9600 8n1 +- SERCOM2 115200 8n1 +- SERCOM4 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMC21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC2 instead of by GPIO. + +Programming and Debugging +************************* + +The SAM C21N Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMC21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: atsamc21n_xpro + :goals: build + :compact: + +#. Connect the SAM C21N Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: atsamc21n_xpro + :goals: flash + :compact: + + You should see "Hello World! atsamc21n_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + https://www.microchip.com/en-us/development-tool/ATSAMC21N-XPRO + +.. _SAM C21 Family Datasheet: + https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/DataSheets/SAM-C20-C21-Family-Data-Sheet-DS60001479J.pdf + +.. _SAM C21N Xplained Pro Schematic: + https://ww1.microchip.com/downloads/en/DeviceDoc/ATSAMC21N_Xplained_Pro_Design_Files.zip diff --git a/boards/arm/atsamc21n_xpro/pre_dt_board.cmake b/boards/arm/atsamc21n_xpro/pre_dt_board.cmake new file mode 100644 index 0000000000000..9be9a0b97715c --- /dev/null +++ b/boards/arm/atsamc21n_xpro/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - /soc/pinmux@41004400 & /soc/gpio@41004400 +# - /soc/pinmux@41004480 & /soc/gpio@41004480 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/atsamc21n_xpro/support/openocd.cfg b/boards/arm/atsamc21n_xpro/support/openocd.cfg new file mode 100644 index 0000000000000..72baa2102f198 --- /dev/null +++ b/boards/arm/atsamc21n_xpro/support/openocd.cfg @@ -0,0 +1,25 @@ +# Copyright (c) 2018 Bryan O'Donoghue +# Copyright (c) 2022 Kamil Serwus +# SPDX-License-Identifier: Apache-2.0 +source [find interface/cmsis-dap.cfg] +transport select swd + +# chip name +set CHIPNAME at91samc21n18a +set ENDIAN little +set CPUTAPID 0x0bc11477 + +source [find target/at91samdXX.cfg] + +reset_config trst_and_srst separate + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/samples/drivers/adc/boards/atsamc21n_xpro.overlay b/samples/drivers/adc/boards/atsamc21n_xpro.overlay new file mode 100644 index 0000000000000..5eec7a475fc4a --- /dev/null +++ b/samples/drivers/adc/boards/atsamc21n_xpro.overlay @@ -0,0 +1,28 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 Argentum Systems Ltd. + */ + +#include + +/ { + zephyr,user { + /* EXT-1, pin 3 ADC(+) */ + io-channels = <&adc0 3>; + }; +}; + +&adc0 { + #address-cells = <1>; + #size-cells = <0>; + + channel@3 { + reg = <3>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = <3>; + }; +};