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Preliminary ESP32 port #517

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merged 10 commits into from Jun 21, 2017

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lpereira commented Jun 15, 2017

This patch set adds preliminary support for ESP32, both as a SoC, and as a board. I haven't compiled the documentation yet, but the individual commit messages contain much of what's necessary to build Zephyr for this board. I'm submitting this series now in order to gather feedback and raise awareness in the ESP32 community.

Most of the legwork for an Xtensa port has been made available in previous versions, so basic things such as threads, timers, and synchronization primitives are all working fine. The philosophers sample is working as expected, for instance.

A lot of things are missing from the port, though, including I/O (no GPIO, I2C, SPI, analog I/O, PWM, etc) and connectivity (WiFi, BT, and BLE). We're working on these, and I hope to have patches implementing some of them soon. Connectivity is going to take more work, though.

OpenOCD should work fine (as long as you're using the fork from Espressif).

@lpereira lpereira requested review from nashif, andrewboie, andyross and pfalcon Jun 15, 2017

@galak

Some cleanups for esp32.sh script

lpereira and others added some commits May 3, 2017

Support for Espressif SDK (ESP32, etc)
Three environment variables must be set to use this variant:

   export ZEPHYR_GCC_VARIANT="espressif"
   export ESP_IDF_PATH=/path/to/esp-idf
   export ESPRESSIF_TOOLCHAIN_PATH=/path/to/xtensa-esp32-elf/

ESP-IDF is the SDK provided by Espressif.  It contains, among other things,
the HAL and header files for registers and ROM functions used by the Zephyr
port.  At this stage, with the exception of the HAL library, none of the
binary blobs provided by ESP-IDF are used.  This can be obtained directly
from Espressif, at <https://github.com/espressif/esp-idf>.

Instructions on how to obtain the toolchain are detailed in the README for
ESP-IDF.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
arch: xtensa: Add ESP32 SoC
Due to the configurable nature of the Xtensa platform, the generic name of
"LX6" cannot be used to describe an SoC as far as Zephyr goes.  So ESP32 is
defined both as a SoC and as a board.

This is based on work by Rajavardhan Gundi.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
boards: xtensa: Add ESP32 board
This is based on the work of Rajavardhan Gundi.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
libc: minimal: Add empty sys/cdefs.h
This header is included by some files provided by ESP-IDF.  Nothing
from this header file is actually used: it's only being added allow
things to compile with the minimal libc.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
drivers: esp32: Add minimal UART driver based on ROM routines
This is a minimal driver enabling console output during the port
bringup.  While the driver works, only one of the three UART devices
are supported, and there isn't any way to change any parameters or
use interrupts.  This will most likely be superceded by a proper
driver after the port has matured.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
xtensa: esp32: place .rodata into DRAM
Until ESP32’s flash cache is utilized, .rodata must be stored in RAM.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
xtensa: esp32: configure default UART using ROM functions
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
arch: xtensa: Use Zephyr configuration options
Unconditionally use CONFIG_SIMULATOR_XTENSA to determine if XT_SIMULATOR
or XT_BOARD should be defined.

If CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, also define XT_CLOCK_FREQ.  This
isn't ideal as the clock frequency might be changed in runtime and this
effectively makes it a constant.

Until we can control the clock frequency in runtime, this will suffice.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
soc: esp32: Define __start as a C function
The first stage bootloader, part of the ESP32 ROM, already sets up
a stack that's sufficient to execute C programs.  So, instead of
implementing __stack() in assembly, do it in C to simplify things
slightly.

This ESP32-specific initialization will perform the following:

  - Disable the watchdog timer that's enabled by the bootloader
  - Move exception handlers to IRAM
  - Disable normal interrupts
  - Disable the second CPU
  - Zero out the BSS segment

Things that might be performed in the future include setting up the
CPU frequency, memory protection regions, and enabling the flash
cache.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
esp32: Use esptool.py to flash with 'make flash'
This flashes Zephyr at 0x1000: that's where the first stage bootloader,
part of the ESP32 ROM, expects to find an "image header".

The second-stage bootloader, part of ESP-IDF, isn't used by the Zephyr
port.  However, the bootloader can be used if desired; please refer to
the ESP-IDF documentation on how to set up partitions tables and use
the bootloader.

The following environment variables will affect the ESP32 flashing
process:

  Variable              Default value
  ESP_DEVICE            /dev/ttyUSB0
  ESP_BAUD_RATE         921600
  ESP_FLASH_SIZE        detect
  ESP_FLASH_FREQ        40m
  ESP_FLASH_MODE        dio
  ESP_TOOL              espidf

It's impossible to determine which serial port the ESP32 board is
connected to, as it uses a generic RS232-USB converter.  The default of
/dev/ttyUSB0 is provided as that's often the assigned name on a Linux
machine without any other such converters.

The baud rate of 921600bps is recommended.  If experiencing issues when
flashing, try halving the value a few times (460800, 230400, 115200,
etc).  It might be necessary to change the flash frequency or the flash
mode; please refer to the esptool documentation for guidance on these
settings.

If ${ESP_TOOL} is set to "espidf", the esptool.py script found within
ESP-IDF will be used.  Otherwise, this variable is handled as a path to
the tool.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
@lpereira

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lpereira Jun 19, 2017

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Rebased and fixed comments.

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lpereira commented Jun 19, 2017

Rebased and fixed comments.

config BOARD_ESP32
bool "ESP32 Development Board"
depends on XTENSA
select BOARD_XTENSA

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@andrewboie

andrewboie Jun 20, 2017

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Ugh, at some point we should just use y/n values of CONFIG_SIMULATOR_XTENSA instead of having both CONFIG_SIMULATOR_XTENSA and CONFIG_BOARD_XTENSA

@andrewboie

andrewboie Jun 20, 2017

Contributor

Ugh, at some point we should just use y/n values of CONFIG_SIMULATOR_XTENSA instead of having both CONFIG_SIMULATOR_XTENSA and CONFIG_BOARD_XTENSA

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lpereira Jun 20, 2017

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This is sort of done inside xtensa_rtos.h now: if CONFIG_SIMULATOR_XTENSA is defined, XT_SIMULATOR is defined; otherwise, XT_BOARD gets defined. This select can be removed from Kconfig.board.

@lpereira

lpereira Jun 20, 2017

Member

This is sort of done inside xtensa_rtos.h now: if CONFIG_SIMULATOR_XTENSA is defined, XT_SIMULATOR is defined; otherwise, XT_BOARD gets defined. This select can be removed from Kconfig.board.

flash)
cmd_flash "$@"
;;
*)

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@andrewboie

andrewboie Jun 20, 2017

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do we plan on adding a 'debugserver' target?

@andrewboie

andrewboie Jun 20, 2017

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do we plan on adding a 'debugserver' target?

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@lpereira

lpereira Jun 20, 2017

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Yes.

@lpereira
/* The watchdog timer is enabled in the bootloader. We're done booting,
* so disable it.
*/
*wdt_rtc_reg &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;

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@andrewboie

andrewboie Jun 20, 2017

Contributor

suggest adding a story in the backlog to implement a WDT driver

@andrewboie

andrewboie Jun 20, 2017

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suggest adding a story in the backlog to implement a WDT driver

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@lpereira

lpereira Jun 20, 2017

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Sure.

@lpereira
default esp32
config IRQ_OFFLOAD_INTNUM
default 7

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@andrewboie

andrewboie Jun 20, 2017

Contributor

Assuming this value has been tested.
If unsure, run tests/kernel/irq_offload

@andrewboie

andrewboie Jun 20, 2017

Contributor

Assuming this value has been tested.
If unsure, run tests/kernel/irq_offload

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@lpereira

lpereira Jun 20, 2017

Member

IRQ offload isn't working yet. I've tried with two IRQ nos. that are available for software interrupts, and all I get is an exception. There are more pressing matters at the moment but this is something that have to be fixed eventually.

@lpereira

lpereira Jun 20, 2017

Member

IRQ offload isn't working yet. I've tried with two IRQ nos. that are available for software interrupts, and all I get is an exception. There are more pressing matters at the moment but this is something that have to be fixed eventually.

@nashif

nashif approved these changes Jun 21, 2017

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