diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/Kconfig.pic32cm_jh01_cpro b/boards/microchip/pic32c/pic32cm_jh01_cpro/Kconfig.pic32cm_jh01_cpro new file mode 100644 index 0000000000000..13a44b6b2b804 --- /dev/null +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/Kconfig.pic32cm_jh01_cpro @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PIC32CM_JH01_CPRO + select SOC_PIC32CM5164JH01100 diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/board.cmake b/boards/microchip/pic32c/pic32cm_jh01_cpro/board.cmake new file mode 100644 index 0000000000000..8485fb61cb2f4 --- /dev/null +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=PIC32CM5164JH" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/board.yml b/boards/microchip/pic32c/pic32cm_jh01_cpro/board.yml new file mode 100644 index 0000000000000..6df521a023343 --- /dev/null +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: pic32cm_jh01_cpro + full_name: PIC32CM JH01 Curiosity Pro + vendor: microchip + socs: + - name: pic32cm5164jh01100 diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/doc/img/pic32cm_jh01_cpro.webp b/boards/microchip/pic32c/pic32cm_jh01_cpro/doc/img/pic32cm_jh01_cpro.webp new file mode 100644 index 0000000000000..6460afc51dfe2 Binary files /dev/null and b/boards/microchip/pic32c/pic32cm_jh01_cpro/doc/img/pic32cm_jh01_cpro.webp differ diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/doc/index.rst b/boards/microchip/pic32c/pic32cm_jh01_cpro/doc/index.rst new file mode 100644 index 0000000000000..81247d7db2a18 --- /dev/null +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/doc/index.rst @@ -0,0 +1,104 @@ +.. zephyr:board:: pic32cm_jh01_cpro + +Overview +******** + +The PIC32CM JH01 Curiosity Pro evaluation kit is a hardware platform +to evaluate the Microchip PIC32CM JH01 microcontroller, and the +evaluation kit part number is EV81X90A. The evaluation kit offers a +set of features that enables the PIC32CM JH01 users to get started with +the PIC32CM JH01 peripherals, and to obtain an understanding of how to +integrate the device in their own design. + +Hardware +******** + +- 100-pin TQFP PIC32CM5164 JH01 microcontroller +- 32.768 kHz crystal oscillator +- 32 MHz crystal oscillator +- 512 KiB flash memory and 64 KiB of RAM +- One yellow user LED +- One green board power LED +- One mechanical user push button +- One reset button +- One driven shield Touch button +- Trust Anchor (TA100) Secure Element +- Virtual COM port (CDC) +- Programming and debugging of on-board PIC32CM JH01 through Serial Wire Debug (SWD) +- Arduino uno connector + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +The `PIC32CM JH01 Curiosity Pro User Guide`_ has detailed information about board connections. + +Programming & Debugging +*********************** + +.. zephyr:board-supported-runners:: + +Flash Using J-Link +================== + +To flash the board using the J-Link debugger, follow the steps below: + +1. Install J-Link Software + + - Download and install the `J-Link software`_ tools from Segger. + - Make sure the installed J-Link executables (e.g., ``JLink``, ``JLinkGDBServer``) + are available in your system's PATH. + +2. Connect the Board + + - Connect the `J32 Debug Probe`_ to the board's **CORTEX DEBUG** header. + - Connect the other end of the J32 Debug Probe to your **host machine (PC)** via USB. + - Connect the DEBUG USB port on the board to your host machine to **power up the board**. + +3. Build the Application + + You can build a sample Zephyr application, such as **Blinky**, using the ``west`` tool. + Run the following commands from your Zephyr workspace: + + .. code-block:: console + + west build -b pic32cm_jh01_cpro -p -s samples/basic/blinky + + This will build the Blinky application for the ``pic32cm_jh01_cpro`` board. + +4. Flash the Device + + Once the build completes, flash the firmware using: + + .. code-block:: console + + west flash + + This uses the default ``jlink`` runner to flash the application to the board. + +5. Observe the Result + + After flashing, **LED0** on the board should start **blinking**, indicating that the + application is running successfully. + +References +********** + +PIC32CM JH01 Product Page: + https://www.microchip.com/en-us/product/PIC32CM5164JH01100 + +PIC32CM JH01 Curiosity Pro evaluation kit Page: + https://www.microchip.com/en-us/development-tool/ev81x90a + +.. _PIC32CM JH01 Curiosity Pro User Guide: + https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/UserGuides/PIC32CM-JH01-Curiosity-Pro-Evaluation-Kit-User-Guide-DS70005482.pdf + +.. _J-Link software: + https://www.segger.com/downloads/jlink + +.. _J32 Debug Probe: + https://www.microchip.com/en-us/development-tool/dv164232 diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.dts b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.dts new file mode 100644 index 0000000000000..be9040dacadb9 --- /dev/null +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.dts @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +/ { + model = "PIC32CM JH01 Curiosity Pro"; + compatible = "pic32cmjh01,cpro", "microchip,pic32cm5164jh01100", "microchip,pic32cm"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + aliases { + led0 = &led0; + sw0 = &button0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&portc 5 GPIO_ACTIVE_HIGH>; + label = "Yellow LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&portb 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@7c000 { + label = "storage"; + reg = <0x0007c000 0x4000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <4000000>; +}; diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.yaml b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.yaml new file mode 100644 index 0000000000000..dd8ebb52b1d8e --- /dev/null +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +identifier: pic32cm_jh01_cpro +name: PIC32CM JH01 Curiosity Pro +type: mcu +arch: arm +toolchain: + - zephyr +flash: 512 +ram: 64 +supported: + - gpio +vendor: microchip diff --git a/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro_defconfig b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro_defconfig new file mode 100644 index 0000000000000..912a8e1042370 --- /dev/null +++ b/boards/microchip/pic32c/pic32cm_jh01_cpro/pic32cm_jh01_cpro_defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_ARM_MPU=y diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 0e1cf4155ed9a..8b4af448cfc97 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -53,6 +53,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_MAX2219X gpio_max2219x.c) zephyr_library_sources_ifdef(CONFIG_GPIO_MAX32 gpio_max32.c) zephyr_library_sources_ifdef(CONFIG_GPIO_MCHP_MEC5 gpio_mchp_mec5.c) zephyr_library_sources_ifdef(CONFIG_GPIO_MCHP_MSS gpio_mchp_mss.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_MCHP_PORT_G1 gpio_mchp_port_g1.c) zephyr_library_sources_ifdef(CONFIG_GPIO_MCP230XX gpio_mcp230xx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_MCP23SXX gpio_mcp23sxx.c) zephyr_library_sources_ifdef(CONFIG_GPIO_MCP23XXX gpio_mcp23xxx.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 87271f0ff9411..29faef6a76293 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -140,6 +140,7 @@ source "drivers/gpio/Kconfig.max14917" source "drivers/gpio/Kconfig.max22017" source "drivers/gpio/Kconfig.max2219x" source "drivers/gpio/Kconfig.max32" +source "drivers/gpio/Kconfig.mchp" source "drivers/gpio/Kconfig.mchp_mss" source "drivers/gpio/Kconfig.mcp23xxx" source "drivers/gpio/Kconfig.mcux" diff --git a/drivers/gpio/Kconfig.mchp b/drivers/gpio/Kconfig.mchp new file mode 100644 index 0000000000000..bdc5aec464f06 --- /dev/null +++ b/drivers/gpio/Kconfig.mchp @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config GPIO_MCHP_PORT_G1 + bool "Microchip PORT G1 GPIO driver" + default y + depends on DT_HAS_MICROCHIP_PORT_G1_GPIO_ENABLED + help + This option enables GPIO driver for group (g1) of PORT peripherals. diff --git a/drivers/gpio/gpio_mchp_port_g1.c b/drivers/gpio/gpio_mchp_port_g1.c new file mode 100644 index 0000000000000..8b06cbbedfd9f --- /dev/null +++ b/drivers/gpio/gpio_mchp_port_g1.c @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file gpio_mchp_port_g1.c + * @brief GPIO driver implementation for Microchip devices. + */ + +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(gpio_mchp_port_g1, CONFIG_GPIO_LOG_LEVEL); + +/****************************************************************************** + * @brief Devicetree definitions + *****************************************************************************/ +#define DT_DRV_COMPAT microchip_port_g1_gpio + +/****************************************************************************** + * @brief Data type definitions + *****************************************************************************/ +/** + * @brief Configuration structure for MCHP GPIO driver + */ +struct gpio_mchp_config { + /* Common GPIO driver configuration */ + struct gpio_driver_config common; + + /* Pointer to port group registers */ + port_group_registers_t *gpio_regs; +}; + +/** + * @brief Runtime data structure for MCHP GPIO driver + */ +struct gpio_mchp_data { + /* Common GPIO driver data */ + struct gpio_driver_data common; + + /* Pointer to device structure */ + const struct device *dev; +}; + +/****************************************************************************** + * @brief Helper functions + *****************************************************************************/ +/** + * Get the current value of the GPIO port. + */ +static inline void gpio_port_get_val(port_group_registers_t *regs, uint32_t *port_val) +{ + *port_val = regs->PORT_IN; +} + +/** + * Set the GPIO port output value with a mask. + */ +static inline void gpio_port_outset_masked(port_group_registers_t *regs, uint32_t mask, + uint32_t value) +{ + regs->PORT_OUT = (regs->PORT_OUT & ~(mask)) | (value & mask); +} + +/** + * Enable input on a specific GPIO pin. + */ +static inline void gpio_enable_input(port_group_registers_t *regs, const uint32_t pin) +{ + regs->PORT_PINCFG[pin] |= PORT_PINCFG_INEN(1); +} + +/** + * Set a specific GPIO pin to high. + */ +static inline void gpio_outset(port_group_registers_t *regs, const uint32_t pin) +{ + regs->PORT_OUTSET = BIT(pin); +} + +/** + * Set a specific GPIO pin to low. + */ +static inline void gpio_outclr(port_group_registers_t *regs, const uint32_t pin) +{ + regs->PORT_OUTCLR = BIT(pin); +} + +/** + * Set the direction of a specific GPIO pin to output. + */ +static inline void gpio_set_dir_output(port_group_registers_t *regs, const uint32_t pin) +{ + regs->PORT_PINCFG[pin] &= ~PORT_PINCFG_INEN(1); + regs->PORT_DIRSET = BIT(pin); +} + +/** + * Set the direction of a specific GPIO pin to input. + */ +static inline void gpio_set_dir_input(port_group_registers_t *regs, const uint32_t pin) +{ + gpio_enable_input(regs, pin); + regs->PORT_DIRCLR = BIT(pin); +} + +/** + * Set the direction of a specific GPIO pin to input output. + */ +static inline void gpio_set_dir_input_output(port_group_registers_t *regs, const uint32_t pin) +{ + gpio_enable_input(regs, pin); + regs->PORT_DIRSET = BIT(pin); +} + +/** + * Enable pull-up/pull-down resistor on a specific GPIO pin. + */ +static inline void gpio_enable_pullup(port_group_registers_t *regs, const uint32_t pin) +{ + regs->PORT_PINCFG[pin] |= PORT_PINCFG_PULLEN(1); +} + +/** + * Check if pull-up/pull-down resistor is enabled on a specific GPIO pin. + */ +static inline bool gpio_is_pullup(port_group_registers_t *regs, const uint32_t pin) +{ + bool is_pull_enabled = false; + + if ((regs->PORT_PINCFG[pin] & PORT_PINCFG_PULLEN(1)) != 0) { + is_pull_enabled = true; + } + + return is_pull_enabled; +} + +/** + * Set multiple GPIO pins to high. + */ +static inline void gpio_port_set_pins_high(port_group_registers_t *regs, const uint32_t pins) +{ + regs->PORT_OUTSET = pins; +} + +/** + * Set multiple GPIO pins to low. + */ +static inline void gpio_port_set_pins_low(port_group_registers_t *regs, const uint32_t pins) +{ + regs->PORT_OUTCLR = pins; +} + +/** + * Toggle multiple GPIO pins. + */ +static inline void gpio_port_toggle_pins(port_group_registers_t *regs, const uint32_t pins) +{ + regs->PORT_OUTTGL = pins; +} + +/** + * Check if a specific GPIO pin is set to high. + */ +static inline bool gpio_is_pin_high(port_group_registers_t *regs, const uint32_t pin) +{ + bool is_output_high = false; + + if ((regs->PORT_OUT & BIT(pin)) != 0) { + is_output_high = true; + } + + return is_output_high; +} + +/** + * Get the direction configuration of the GPIO port. + */ +static inline uint32_t gpio_port_get_dir(port_group_registers_t *regs) +{ + return regs->PORT_DIR; +} + +/** + * Check if a specific GPIO pin is configured as output. + */ +static inline bool gpio_is_pin_output(port_group_registers_t *regs, const uint32_t pin) +{ + bool is_output = false; + + if ((gpio_port_get_dir(regs) & BIT(pin)) != 0) { + is_output = true; + } + + return is_output; +} + +/** + * Get the pins configured as input. + */ +static inline uint32_t gpio_port_get_input_pins(port_group_registers_t *regs) +{ + uint32_t pin_id; + uint32_t port_input = 0; + + for (pin_id = 0; pin_id < 32; pin_id++) { + if (((regs->PORT_PINCFG[pin_id] & PORT_PINCFG_INEN(1)) != 0)) { + port_input |= BIT(pin_id); + } + } + + return port_input; +} + +/** + * Get the pins configured as output. + */ +static inline uint32_t gpio_port_get_output_pins(port_group_registers_t *regs) +{ + uint32_t port_output = 0; + + port_output = gpio_port_get_dir(regs); + + return port_output; +} + +/** + * Disconnect the GPIO pin. + */ +static inline void gpio_disconnect(port_group_registers_t *regs, const uint32_t pin) +{ + /* Disable pull-up/pull-down resistor on a specific GPIO pin. */ + regs->PORT_PINCFG[pin] &= ~PORT_PINCFG_PULLEN(1); + + /* Disable input on a specific GPIO pin. */ + regs->PORT_PINCFG[pin] &= ~PORT_PINCFG_INEN(1); + regs->PORT_DIRCLR = BIT(pin); +} + +/** + * Configure GPIO pin as input + */ +static int gpio_configure_input(port_group_registers_t *gpio_reg, gpio_pin_t pin, + gpio_flags_t flags) +{ + /* Configure the pin as input if requested */ + gpio_set_dir_input(gpio_reg, pin); + + /* Configure pull-up or pull-down if requested */ + if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) { + gpio_enable_pullup(gpio_reg, pin); + + if (flags & GPIO_PULL_UP) { + gpio_outset(gpio_reg, pin); + } else { + gpio_outclr(gpio_reg, pin); + } + } + + return 0; +} + +/** + * Configure GPIO pin as output + */ +static int gpio_configure_output(port_group_registers_t *gpio_reg, gpio_pin_t pin, + gpio_flags_t flags) +{ + int retval = 0; + + /* Output is incompatible with pull-up or pull-down */ + if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) { + retval = -ENOTSUP; + } else { + /* Set initial output state if specified */ + if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) { + gpio_outclr(gpio_reg, pin); + } else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { + gpio_outset(gpio_reg, pin); + } else { + /* No init value requested */ + retval = 0; + } + } + + /* Set the pin as output */ + gpio_set_dir_output(gpio_reg, pin); + + return retval; +} + +/****************************************************************************** + * @brief API functions + *****************************************************************************/ +/** + * @brief Configure a GPIO pin + * + * @param dev Pointer to the device structure + * @param pin Pin number to configure + * @param flags Configuration flags + * @retval 0 on success + * @retval ENOTSUP If any of the configuration options is not supported + */ +static int gpio_mchp_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +{ + const struct gpio_mchp_config *config = dev->config; + port_group_registers_t *gpio_reg = config->gpio_regs; + gpio_flags_t io_flags = flags & (GPIO_INPUT | GPIO_OUTPUT); + int retval = 0; + + /* Disable the pinmux functionality as its gpio */ + gpio_reg->PORT_PINCFG[pin] &= (uint8_t)~PORT_PINCFG_PMUXEN_Msk; + + if (io_flags == GPIO_DISCONNECTED) { + + /* Disconnect the gpio */ + gpio_disconnect(gpio_reg, pin); + } + + /* Check for single-ended mode configuration */ + else if (flags & GPIO_SINGLE_ENDED) { + retval = -ENOTSUP; + } + + /* Configure the pin as input and output if requested */ + else if (io_flags == (GPIO_INPUT | GPIO_OUTPUT)) { + gpio_set_dir_input_output(gpio_reg, pin); + + /* Set initial output state if specified */ + if (flags & GPIO_OUTPUT_INIT_LOW) { + gpio_outclr(gpio_reg, pin); + } else if (flags & GPIO_OUTPUT_INIT_HIGH) { + gpio_outset(gpio_reg, pin); + } else { + /* No init value requested */ + retval = 0; + } + } else if (flags & GPIO_INPUT) { + retval = gpio_configure_input(gpio_reg, pin, flags); + } else if (flags & GPIO_OUTPUT) { + retval = gpio_configure_output(gpio_reg, pin, flags); + } else { + /* Catch-all for unexpected flag combinations */ + retval = -ENOTSUP; + } + + return retval; +} + +/** + * @brief Get raw port value + * + * @param dev Pointer to the device structure + * @param value Pointer to store the port value + * @retval 0 on success + */ +static int gpio_mchp_port_get_raw(const struct device *dev, gpio_port_value_t *value) +{ + const struct gpio_mchp_config *config = dev->config; + port_group_registers_t *gpio_reg = config->gpio_regs; + + /* Read the input value of the port */ + gpio_port_get_val(gpio_reg, value); + + return 0; +} + +/** + * @brief Set masked raw port value + * + * @param dev Pointer to the device structure + * @param mask Mask of pins to set + * @param value Value to set + * @retval 0 on success + */ +static int gpio_mchp_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, + gpio_port_value_t value) +{ + const struct gpio_mchp_config *config = dev->config; + port_group_registers_t *gpio_reg = config->gpio_regs; + + /* Set the output value of the port with the specified mask */ + gpio_port_outset_masked(gpio_reg, mask, value); + + return 0; +} + +/** + * @brief Set bits in raw port value + * + * @param dev Pointer to the device structure + * @param pins Pins to set + * @retval 0 on success + */ +static int gpio_mchp_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_mchp_config *config = dev->config; + port_group_registers_t *gpio_reg = config->gpio_regs; + + /* Set the specified pins in the output register */ + gpio_port_set_pins_high(gpio_reg, pins); + + return 0; +} + +/** + * @brief Clear bits in raw port value + * + * @param dev Pointer to the device structure + * @param pins Pins to clear + * @retval 0 on success + */ +static int gpio_mchp_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_mchp_config *config = dev->config; + port_group_registers_t *gpio_reg = config->gpio_regs; + + /* Clear the specified pins in the output register */ + gpio_port_set_pins_low(gpio_reg, pins); + + return 0; +} + +/** + * @brief Toggle bits in raw port value + * + * @param dev Pointer to the device structure + * @param pins Pins to toggle + * @retval 0 on success + */ +static int gpio_mchp_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_mchp_config *config = dev->config; + port_group_registers_t *gpio_reg = config->gpio_regs; + + /* Toggle the specified pins in the output register */ + gpio_port_toggle_pins(gpio_reg, pins); + + return 0; +} + +#ifdef CONFIG_GPIO_GET_CONFIG +/** + * @brief Get the configuration of a specific GPIO pin + * + * This function retrieves the configuration flags of a specified GPIO pin. + * + * @param dev Pointer to the device structure + * @param pin The pin number to get the configuration for + * @param out_flags Pointer to store the retrieved configuration flags + * @retval 0 on success + */ +static int gpio_mchp_pin_get_config(const struct device *dev, gpio_pin_t pin, + gpio_flags_t *out_flags) +{ + const struct gpio_mchp_config *config = dev->config; + port_group_registers_t *gpio_reg = config->gpio_regs; + struct gpio_mchp_data *data = dev->data; + gpio_flags_t flags = 0; + + /* flag to check if the pin is configured as an output */ + bool is_output = gpio_is_pin_output(gpio_reg, pin); + + /* flag to check if pull-up or pull-down resistors are enabled */ + bool is_pull_enabled = gpio_is_pullup(gpio_reg, pin); + + /* flag to check if the output is set to high */ + bool is_output_high = gpio_is_pin_high(gpio_reg, pin); + + /* Check if the pin is configured as active low */ + bool is_active_low = data->common.invert & (gpio_port_pins_t)BIT(pin); + + /* Check if the pin is configured as an output */ + if (is_output) { + flags |= GPIO_OUTPUT; + flags |= is_output_high ? GPIO_OUTPUT_INIT_HIGH : GPIO_OUTPUT_INIT_LOW; + } else { + flags |= GPIO_INPUT; + + /* Check if pull-up or pull-down resistors are enabled */ + if (is_pull_enabled) { + flags |= is_output_high ? GPIO_PULL_UP : GPIO_PULL_DOWN; + } + } + + /* Check if the pin is configured as active low */ + flags |= is_active_low ? GPIO_ACTIVE_LOW : GPIO_ACTIVE_HIGH; + + *out_flags = flags; + + return 0; +} +#endif /* CONFIG_GPIO_GET_CONFIG */ + +#ifdef CONFIG_GPIO_GET_DIRECTION +/** + * @brief Get the direction of GPIO pins in a port. + * + * This function retrieves the direction (input or output) of the specified GPIO pins in a port. + * + * @param dev Pointer to the device structure for the driver instance. + * @param map Bitmask representing the pins to check. + * @param inputs Pointer to store the bitmask of input pins (can be NULL). + * @param outputs Pointer to store the bitmask of output pins (can be NULL). + * + * @retval 0 on success + */ +static int gpio_mchp_port_get_direction(const struct device *dev, gpio_port_pins_t map, + gpio_port_pins_t *inputs, gpio_port_pins_t *outputs) +{ + /* Get the device configuration */ + const struct gpio_mchp_config *config = dev->config; + + /* Get the GPIO register base address */ + port_group_registers_t *gpio_reg = config->gpio_regs; + + map &= config->common.port_pin_mask; + + if (inputs != NULL) { + /* Get the input pins */ + *inputs = map & (gpio_port_get_input_pins(gpio_reg)); + } + + if (outputs != NULL) { + /* Get the output pins */ + *outputs = map & (gpio_port_get_output_pins(gpio_reg)); + } + + return 0; +} + +#endif /* CONFIG_GPIO_GET_DIRECTION */ + +/****************************************************************************** + * @brief Zephyr driver instance creation + *****************************************************************************/ +/** + * @brief GPIO driver API structure + */ +static DEVICE_API(gpio, gpio_mchp_api) = { + .pin_configure = gpio_mchp_configure, + .port_get_raw = gpio_mchp_port_get_raw, + .port_set_masked_raw = gpio_mchp_port_set_masked_raw, + .port_set_bits_raw = gpio_mchp_port_set_bits_raw, + .port_clear_bits_raw = gpio_mchp_port_clear_bits_raw, + .port_toggle_bits = gpio_mchp_port_toggle_bits, +#ifdef CONFIG_GPIO_GET_CONFIG + .pin_get_config = gpio_mchp_pin_get_config, +#endif +#ifdef CONFIG_GPIO_GET_DIRECTION + .port_get_direction = gpio_mchp_port_get_direction, +#endif +}; + +/** + * @brief Initialize the GPIO driver + * + * @param dev Pointer to the device structure + * @retval 0 on success + */ +static int gpio_mchp_init(const struct device *dev) +{ + return 0; +} + +/* Define GPIO port configuration macro */ +/* clang-format off */ +#define GPIO_PORT_CONFIG(idx) \ + static const struct gpio_mchp_config gpio_mchp_config_##idx = { \ + .common = { \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \ + }, \ + .gpio_regs = (port_group_registers_t *)DT_INST_REG_ADDR(idx), \ + }; \ + static struct gpio_mchp_data gpio_mchp_data_##idx; \ + DEVICE_DT_DEFINE(DT_INST(idx, DT_DRV_COMPAT), gpio_mchp_init, NULL, &gpio_mchp_data_##idx, \ + &gpio_mchp_config_##idx, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \ + &gpio_mchp_api); +/* clang-format on */ + +/* Use DT_INST_FOREACH_STATUS_OKAY to iterate over GPIO instances */ +DT_INST_FOREACH_STATUS_OKAY(GPIO_PORT_CONFIG) diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_1216_jh.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_1216_jh.dtsi new file mode 100644 index 0000000000000..9620929cc4a74 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_1216_jh.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Memory configuration: Flash size, RAM Size and Data Flash size for 1216 devices */ + +/ { + soc { + flash0: flash@0 { + reg = <0x0 DT_SIZE_K(128)>; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(16)>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_2532_jh.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_2532_jh.dtsi new file mode 100644 index 0000000000000..7615c81e00a2f --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_2532_jh.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Memory configuration: Flash size, RAM Size, Data Flash size + * and additional nodes for 2532 memory variants + */ + +/ { + soc { + flash0: flash@0 { + reg = <0x0 DT_SIZE_K(256)>; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(32)>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_5164_jh.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_5164_jh.dtsi new file mode 100644 index 0000000000000..e6e8ba179095a --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_5164_jh.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Memory configuration: Flash size, RAM Size, Data Flash size + * and additional nodes for 5164 memory variants + */ + +/ { + soc { + flash0: flash@0 { + reg = <0x0 DT_SIZE_K(512)>; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh.dtsi new file mode 100644 index 0000000000000..13559446c1da9 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Common SoC definitions shared across all PIC32CM JH devices */ + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m0+"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv6m-mpu"; + reg = <0xe000ed90 0x2c>; + }; + }; + }; + + soc { + flash0: flash@0 { + compatible = "soc-nv-flash"; + write-block-size = <4>; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + porta: gpio@41000000 { + compatible = "microchip,port-g1-gpio"; + reg = <0x41000000 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_100.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_100.dtsi new file mode 100644 index 0000000000000..4344da122c19c --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_100.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Device-tree nodes specific to 100-pin package variants */ + +#include + +/ { + soc { + portb: gpio@41000080 { + compatible = "microchip,port-g1-gpio"; + reg = <0x41000080 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + + portc: gpio@41000100 { + compatible = "microchip,port-g1-gpio"; + reg = <0x41000100 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_32.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_32.dtsi new file mode 100644 index 0000000000000..06d3bb0bb2f8b --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_32.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Device-tree nodes specific to 32-pin package variants */ + +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_48.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_48.dtsi new file mode 100644 index 0000000000000..80e9afa5384be --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_48.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Device-tree nodes specific to 48-pin package variants */ + +#include + +/ { + soc { + portb: gpio@41000080 { + compatible = "microchip,port-g1-gpio"; + reg = <0x41000080 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_64.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_64.dtsi new file mode 100644 index 0000000000000..f3b93a41dc5de --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh_64.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Device-tree nodes specific to 64-pin package variants */ + +#include + +/ { + soc { + portb: gpio@41000080 { + compatible = "microchip,port-g1-gpio"; + reg = <0x41000080 0x80>; + gpio-controller; + #gpio-cells = <2>; + #microchip,pin-cells = <2>; + }; + }; +}; diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00032.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00032.dtsi new file mode 100644 index 0000000000000..78c06eeb74458 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00032.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00048.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00048.dtsi new file mode 100644 index 0000000000000..3b8aea9c72fe5 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00048.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00064.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00064.dtsi new file mode 100644 index 0000000000000..1f25918d5ead9 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00064.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00100.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00100.dtsi new file mode 100644 index 0000000000000..8b164531b3736 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm2532jh00100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00032.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00032.dtsi new file mode 100644 index 0000000000000..e5727f06ee5c6 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00032.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00048.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00048.dtsi new file mode 100644 index 0000000000000..a185c33dab6ca --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00048.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00064.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00064.dtsi new file mode 100644 index 0000000000000..49c0b9978df75 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00064.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00100.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00100.dtsi new file mode 100644 index 0000000000000..ffe6b33b866d5 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh00/pic32cm5164jh00100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm1216jh01032.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm1216jh01032.dtsi new file mode 100644 index 0000000000000..f9f932d791d7d --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm1216jh01032.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm1216jh01048.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm1216jh01048.dtsi new file mode 100644 index 0000000000000..b9d842f8ceba9 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm1216jh01048.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01032.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01032.dtsi new file mode 100644 index 0000000000000..78c06eeb74458 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01032.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01048.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01048.dtsi new file mode 100644 index 0000000000000..3b8aea9c72fe5 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01048.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01064.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01064.dtsi new file mode 100644 index 0000000000000..1f25918d5ead9 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01064.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01100.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01100.dtsi new file mode 100644 index 0000000000000..8b164531b3736 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm2532jh01100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01032.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01032.dtsi new file mode 100644 index 0000000000000..e5727f06ee5c6 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01032.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01048.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01048.dtsi new file mode 100644 index 0000000000000..a185c33dab6ca --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01048.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01064.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01064.dtsi new file mode 100644 index 0000000000000..49c0b9978df75 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01064.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01100.dtsi b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01100.dtsi new file mode 100644 index 0000000000000..ffe6b33b866d5 --- /dev/null +++ b/dts/arm/microchip/pic32c/pic32cm_jh/pic32cm_jh01/pic32cm5164jh01100.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include diff --git a/dts/bindings/gpio/microchip,port-g1-gpio.yaml b/dts/bindings/gpio/microchip,port-g1-gpio.yaml new file mode 100644 index 0000000000000..05ea54aa6ab14 --- /dev/null +++ b/dts/bindings/gpio/microchip,port-g1-gpio.yaml @@ -0,0 +1,39 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +title: Microchip Port G1 GPIO + +description: | + GPIO controller for the Microchip Port Group 1 (G1) + + Group g1 PORT GPIO driver supports following hardware peripherals: + - module name="PORT" id="U2210" version="2.2.0" + - module name="PORT" id="U2210" version="3.1.0" + +compatible: "microchip,port-g1-gpio" + +include: + - name: base.yaml + - name: gpio-controller.yaml + +properties: + reg: + required: true + + "#gpio-cells": + const: 2 + + "#microchip,pin-cells": + type: int + required: true + const: 2 + description: | + Number of items to expect in a microchip,pins specifier + +gpio-cells: + - pin + - flags + +microchip,pin-cells: + - pin + - peripheral diff --git a/modules/Kconfig.microchip b/modules/Kconfig.microchip index 7497d99ead0a5..f7e2306387378 100644 --- a/modules/Kconfig.microchip +++ b/modules/Kconfig.microchip @@ -10,3 +10,6 @@ config HAS_MPFS_HAL config HAS_MEC5_HAL bool "Microchip MEC5 HAL drivers support" + +config PIC32C + bool diff --git a/soc/microchip/pic32c/pic32cm_jh/CMakeLists.txt b/soc/microchip/pic32c/pic32cm_jh/CMakeLists.txt new file mode 100644 index 0000000000000..3742da6443b22 --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(common) +zephyr_include_directories(${SOC_SERIES}) diff --git a/soc/microchip/pic32c/pic32cm_jh/Kconfig b/soc/microchip/pic32c/pic32cm_jh/Kconfig new file mode 100644 index 0000000000000..5628263dc3d15 --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_PIC32CM_JH + select ARM + select PIC32C + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select SOC_RESET_HOOK diff --git a/soc/microchip/pic32c/pic32cm_jh/Kconfig.defconfig b/soc/microchip/pic32c/pic32cm_jh/Kconfig.defconfig new file mode 100644 index 0000000000000..0ea894cf58429 --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_PIC32CM_JH + +config NUM_IRQS + default 32 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif # SOC_FAMILY_MICROCHIP_PIC32CM_JH diff --git a/soc/microchip/pic32c/pic32cm_jh/Kconfig.soc b/soc/microchip/pic32c/pic32cm_jh/Kconfig.soc new file mode 100644 index 0000000000000..da517d2b417e0 --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/Kconfig.soc @@ -0,0 +1,21 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_PIC32CM_JH + bool + +config SOC_FAMILY + default "microchip_pic32cm_jh" if SOC_FAMILY_MICROCHIP_PIC32CM_JH + +# List of Peripheral IPs available in SOC_FAMILY_MICROCHIP_PIC32CM_JH family +if SOC_FAMILY_MICROCHIP_PIC32CM_JH + +config GPIO_MCHP_PORT_U2210_3_1_0 + bool + default y + help + Enable PORT GPIO peripheral IP version id="U2210" version="3.1.0". + +endif # SOC_FAMILY_MICROCHIP_PIC32CM_JH + +rsource "*/Kconfig.soc" diff --git a/soc/microchip/pic32c/pic32cm_jh/common/CMakeLists.txt b/soc/microchip/pic32c/pic32cm_jh/common/CMakeLists.txt new file mode 100644 index 0000000000000..dd55f52055c19 --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/common/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/pic32c/pic32cm_jh/common/soc.c b/soc/microchip/pic32c/pic32cm_jh/common/soc.c new file mode 100644 index 0000000000000..99a494095687b --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/common/soc.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file soc.c + * @brief Microchip PIC32CM JH family initialization code + */ + +#include + +#define SRAM0_NODE DT_CHOSEN(zephyr_sram) +#define SRAM0_BASE DT_REG_ADDR(SRAM0_NODE) +#define SRAM0_SIZE DT_REG_SIZE(SRAM0_NODE) + +/** + * @brief Initialize (clear) the SRAM region defined by DT node sram0. + * + * After reset, SRAM content (data + ECC bits) is random and ECC is enabled by default. + * Any 8-bit or 16-bit write may trigger single or double ECC errors due to the internal + * read-modify-write of 32-bit words. Therefore, the SRAM must be initialized before use + * to ensure ECC correctness. + * + * This function performs 32-bit writes to clear the entire SRAM safely. + * It is intended for reuse across all SoCs that feature ECC-enabled SRAM. + * + * @note + * This SRAM initialization is specific to device families with ECC-enabled SRAM + * and should not be included in the generic architecture configuration. + * The function is best invoked from the soc_reset_hook of the relevant device family, + * which is called before stack initialization and before transitioning to C code. + */ +static void soc_mchp_sram_ecc_initialization(void) +{ + volatile uint32_t *ram_start = (uint32_t *)SRAM0_BASE; + volatile uint32_t *ram_end = (uint32_t *)(SRAM0_BASE + SRAM0_SIZE); + + for (; ram_start < ram_end; ++ram_start) { + *ram_start = 0U; + } +} + +/** + * @brief Reset hook to run SoC-specific initialization. + * + * This is invoked very early at reset. + */ +void soc_reset_hook(void) +{ + soc_mchp_sram_ecc_initialization(); +} diff --git a/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh00/Kconfig.soc b/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh00/Kconfig.soc new file mode 100644 index 0000000000000..3da84ca3a6eca --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh00/Kconfig.soc @@ -0,0 +1,53 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PIC32CM_JH00 + bool + select SOC_FAMILY_MICROCHIP_PIC32CM_JH + help + Enable support for Microchip PIC32CM JH00 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "pic32cm_jh00" if SOC_SERIES_PIC32CM_JH00 + +config SOC_PIC32CM2532JH00032 + bool + select SOC_SERIES_PIC32CM_JH00 + +config SOC_PIC32CM5164JH00032 + bool + select SOC_SERIES_PIC32CM_JH00 + +config SOC_PIC32CM2532JH00048 + bool + select SOC_SERIES_PIC32CM_JH00 + +config SOC_PIC32CM5164JH00048 + bool + select SOC_SERIES_PIC32CM_JH00 + +config SOC_PIC32CM2532JH00064 + bool + select SOC_SERIES_PIC32CM_JH00 + +config SOC_PIC32CM5164JH00064 + bool + select SOC_SERIES_PIC32CM_JH00 + +config SOC_PIC32CM2532JH00100 + bool + select SOC_SERIES_PIC32CM_JH00 + +config SOC_PIC32CM5164JH00100 + bool + select SOC_SERIES_PIC32CM_JH00 + +config SOC + default "pic32cm2532jh00032" if SOC_PIC32CM2532JH00032 + default "pic32cm5164jh00032" if SOC_PIC32CM5164JH00032 + default "pic32cm2532jh00048" if SOC_PIC32CM2532JH00048 + default "pic32cm5164jh00048" if SOC_PIC32CM5164JH00048 + default "pic32cm2532jh00064" if SOC_PIC32CM2532JH00064 + default "pic32cm5164jh00064" if SOC_PIC32CM5164JH00064 + default "pic32cm2532jh00100" if SOC_PIC32CM2532JH00100 + default "pic32cm5164jh00100" if SOC_PIC32CM5164JH00100 diff --git a/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh00/soc.h b/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh00/soc.h new file mode 100644 index 0000000000000..53b6b57f7a717 --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh00/soc.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SOC_MICROCHIP_PIC32CM_JH00_SOC_H_ +#define SOC_MICROCHIP_PIC32CM_JH00_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#if defined(CONFIG_SOC_PIC32CM2532JH00032) +#include +#elif defined(CONFIG_SOC_PIC32CM5164JH00032) +#include +#elif defined(CONFIG_SOC_PIC32CM2532JH00048) +#include +#elif defined(CONFIG_SOC_PIC32CM5164JH00048) +#include +#elif defined(CONFIG_SOC_PIC32CM2532JH00064) +#include +#elif defined(CONFIG_SOC_PIC32CM5164JH00064) +#include +#elif defined(CONFIG_SOC_PIC32CM2532JH00100) +#include +#elif defined(CONFIG_SOC_PIC32CM5164JH00100) +#include +#else +#error "Library does not support the specified device." +#endif + +#endif /* _ASMLANGUAGE */ + +#endif /* SOC_MICROCHIP_PIC32CM_JH00_SOC_H_ */ diff --git a/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh01/Kconfig.soc b/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh01/Kconfig.soc new file mode 100644 index 0000000000000..c7c1511e60b03 --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh01/Kconfig.soc @@ -0,0 +1,63 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PIC32CM_JH01 + bool + select SOC_FAMILY_MICROCHIP_PIC32CM_JH + help + Enable support for Microchip PIC32CM JH01 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "pic32cm_jh01" if SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM2532JH01032 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM5164JH01032 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM2532JH01048 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM5164JH01048 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM2532JH01064 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM5164JH01064 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM2532JH01100 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM5164JH01100 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM1216JH01032 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC_PIC32CM1216JH01048 + bool + select SOC_SERIES_PIC32CM_JH01 + +config SOC + default "pic32cm2532jh01032" if SOC_PIC32CM2532JH01032 + default "pic32cm5164jh01032" if SOC_PIC32CM5164JH01032 + default "pic32cm2532jh01048" if SOC_PIC32CM2532JH01048 + default "pic32cm5164jh01048" if SOC_PIC32CM5164JH01048 + default "pic32cm2532jh01064" if SOC_PIC32CM2532JH01064 + default "pic32cm5164jh01064" if SOC_PIC32CM5164JH01064 + default "pic32cm2532jh01100" if SOC_PIC32CM2532JH01100 + default "pic32cm5164jh01100" if SOC_PIC32CM5164JH01100 + default "pic32cm1216jh01032" if SOC_PIC32CM1216JH01032 + default "pic32cm1216jh01048" if SOC_PIC32CM1216JH01048 diff --git a/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh01/soc.h b/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh01/soc.h new file mode 100644 index 0000000000000..c8c82b1333dc5 --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/pic32cm_jh01/soc.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SOC_MICROCHIP_PIC32CM_JH01_SOC_H_ +#define SOC_MICROCHIP_PIC32CM_JH01_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#if defined(CONFIG_SOC_PIC32CM2532JH01032) +#include +#elif defined(CONFIG_SOC_PIC32CM5164JH01032) +#include +#elif defined(CONFIG_SOC_PIC32CM2532JH01048) +#include +#elif defined(CONFIG_SOC_PIC32CM5164JH01048) +#include +#elif defined(CONFIG_SOC_PIC32CM2532JH01064) +#include +#elif defined(CONFIG_SOC_PIC32CM5164JH01064) +#include +#elif defined(CONFIG_SOC_PIC32CM2532JH01100) +#include +#elif defined(CONFIG_SOC_PIC32CM5164JH01100) +#include +#elif defined(CONFIG_SOC_PIC32CM1216JH01032) +#include +#elif defined(CONFIG_SOC_PIC32CM1216JH01048) +#include +#else +#error "Library does not support the specified device." +#endif + +#endif /* _ASMLANGUAGE */ + +#endif /* SOC_MICROCHIP_PIC32CM_JH01_SOC_H_ */ diff --git a/soc/microchip/pic32c/pic32cm_jh/soc.yml b/soc/microchip/pic32c/pic32cm_jh/soc.yml new file mode 100644 index 0000000000000..362a060020e74 --- /dev/null +++ b/soc/microchip/pic32c/pic32cm_jh/soc.yml @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +family: +- name: microchip_pic32cm_jh + series: + - name: pic32cm_jh00 + socs: + - name: pic32cm2532jh00032 + - name: pic32cm5164jh00032 + - name: pic32cm2532jh00048 + - name: pic32cm5164jh00048 + - name: pic32cm2532jh00064 + - name: pic32cm5164jh00064 + - name: pic32cm2532jh00100 + - name: pic32cm5164jh00100 + - name: pic32cm_jh01 + socs: + - name: pic32cm2532jh01032 + - name: pic32cm5164jh01032 + - name: pic32cm2532jh01048 + - name: pic32cm5164jh01048 + - name: pic32cm2532jh01064 + - name: pic32cm5164jh01064 + - name: pic32cm2532jh01100 + - name: pic32cm5164jh01100 + - name: pic32cm1216jh01032 + - name: pic32cm1216jh01048 diff --git a/west.yml b/west.yml index 945fa7fed0b44..0e56c9a27db79 100644 --- a/west.yml +++ b/west.yml @@ -195,7 +195,7 @@ manifest: groups: - hal - name: hal_microchip - revision: 2c5eb6b7b9ef3a442ff9d9536fbc63b2028c2d0e + revision: e5fe6469afc53d7aefcc74377dd99ce20428d42b path: modules/hal/microchip groups: - hal