diff --git a/boards/nxp/frdm_mcxe31b/CMakeLists.txt b/boards/nxp/frdm_mcxe31b/CMakeLists.txt new file mode 100644 index 0000000000000..8abb2d2591260 --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_MCXE31X_BOOT_HEADER) + zephyr_library_sources(boot_header/boot_header.c) + zephyr_library_include_directories(boot_header) +endif() diff --git a/boards/nxp/frdm_mcxe31b/Kconfig b/boards/nxp/frdm_mcxe31b/Kconfig new file mode 100644 index 0000000000000..1521068168d5b --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/Kconfig @@ -0,0 +1,11 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config NXP_MCXE31X_BOOT_HEADER + bool "MCXE31x boot header support" + default y + help + Enable this option to include the MCXE31x boot header in the final + image. The boot header is required for proper operation of the + on-chip bootloader. + See the MCXE31x reference manual for more details. diff --git a/boards/nxp/frdm_mcxe31b/Kconfig.frdm_mcxe31b b/boards/nxp/frdm_mcxe31b/Kconfig.frdm_mcxe31b new file mode 100644 index 0000000000000..0a5bb955a9b88 --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/Kconfig.frdm_mcxe31b @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXE31B + select SOC_PART_NUMBER_MCXE31BMPB diff --git a/boards/nxp/frdm_mcxe31b/board.cmake b/boards/nxp/frdm_mcxe31b/board.cmake new file mode 100644 index 0000000000000..2226277c530be --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/board.cmake @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(jlink "--device=MCXE31B") +board_runner_args(linkserver "--device=MCXE31B:FRDM-MCXE31B") + +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/frdm_mcxe31b/board.yml b/boards/nxp/frdm_mcxe31b/board.yml new file mode 100644 index 0000000000000..f4030712e3c2b --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/board.yml @@ -0,0 +1,6 @@ +board: + name: frdm_mcxe31b + full_name: FRDM-MCXE31B + vendor: nxp + socs: + - name: mcxe31b diff --git a/boards/nxp/frdm_mcxe31b/boot_header/boot_header.c b/boards/nxp/frdm_mcxe31b/boot_header/boot_header.c new file mode 100644 index 0000000000000..691d5af778e56 --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/boot_header/boot_header.c @@ -0,0 +1,91 @@ +/* + * Copyright 2025 NXP + * + * SPDXLicense-Identifier: Apache-2.0 + */ + +#include "boot_header.h" +#include "fsl_common.h" + +/****************************************************************************** + * External references + ******************************************************************************/ +#if defined(CONFIG_NXP_MCXE31X_BOOT_HEADER) && (CONFIG_NXP_MCXE31X_BOOT_HEADER != 0U) + +extern void *const _vector_start; + +/****************************************************************************** + * Boot Header + ******************************************************************************/ +typedef struct image_vector_table { + uint32_t header; /* header */ + uint32_t boot_config; /* Boot configuration Word */ + const uint32_t reserved1; /* Reserved */ + const uint32_t *cm7_0_start_address; /* Start address of CM7_0 Core */ + const uint32_t reserved2; /* Reserved */ + const uint32_t *reserved3; /* Reserved */ + const uint32_t reserved4; /* Reserved */ + const uint32_t *reserved5; /* Reserved */ + const uint32_t *reserved6; /* Reserved */ + const uint32_t *lcc_config; /* Address of LC config */ + uint8_t reserved7[216]; /* Reserved for future use */ +} ivt_t; + +/****************************************************************************** + * SBAF definitions + ******************************************************************************/ +/* CM7_0_ENABLE: */ +/* 0- Cortex-M7_0 application core clock gated after boot */ +/* 1- Cortex-M7_0 application core clock un-gated after boot */ +#define CM7_0_ENABLE_MASK 1U + +/* Control the boot flow of the application: */ +/* 0- Non-Secure Boot- Application image is started by SBAF without any */ +/* authentication in parallel to HSE firmware. */ +/* 1- Secure Boot- Application image is executed by HSE firmware after the */ +/* authentication. SBAF only starts the HSE firmware after successful */ +/* authentication. */ +#define BOOT_SEQ_MASK 8U + +/* APP_SWT_INIT: Control SWT0 before starting application core(s): */ +/* 0- Disable. */ +/* 1- Enable. SBAF initializes SWT0 before enabling application cores. */ +/* SBAF scans this bit only when BOOT_SEQ bit is 0. */ +#define APP_SWT_INIT_MASK 32U + +/*! + * @brief Sets register field in peripheral configuration structure. + * @details This macro sets register field mask in the peripheral + * configuration structure. + * @param mask Register field to be set. + * @note Implemented as a macro. + */ +#define SET(mask) (mask) + +/*! + * @brief Clears register field in peripheral configuration structure. + * @details This macro clears register field mask in the peripheral + * configuration structure. + * @param mask Register field to be cleared. + * @note Implemented as a macro. + */ +#define CLR(mask) 0 + +const ivt_t _boot_header __attribute__((used, section(".boot_header"))) = { + .header = 0x5AA55AA5, + .boot_config = SET(CM7_0_ENABLE_MASK) | /* booting core is core0 */ + CLR(BOOT_SEQ_MASK) | /* unsecure boot is only supported */ + CLR(APP_SWT_INIT_MASK), /* SWT0 is not setup by BAF */ + .cm7_0_start_address = (const uint32_t *)&_vector_start, + .lcc_config = (const uint32_t *)&lc_config}; + +/****************************************************************************** + * Default configurations that can be overridden by strong definitions + ******************************************************************************/ + +__WEAK const boot_lc_config_t lc_config = 0xffffffff; + +#endif /* CONFIG_NXP_MCXE31X_BOOT_HEADER */ +/****************************************************************************** + * End of module + ******************************************************************************/ diff --git a/boards/nxp/frdm_mcxe31b/boot_header/boot_header.h b/boards/nxp/frdm_mcxe31b/boot_header/boot_header.h new file mode 100644 index 0000000000000..3684d0e7744b0 --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/boot_header/boot_header.h @@ -0,0 +1,19 @@ +/* + * Copyright 2025 NXP + * + * SPDXLicense-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_BOOT_HEADER_H_ +#define ZEPHYR_INCLUDE_BOOT_HEADER_H_ + +#include "fsl_common.h" + +/****************************************************************************** + * Configuration structure definition * + ******************************************************************************/ + +typedef uint32_t boot_lc_config_t; +extern const boot_lc_config_t lc_config; + +#endif /* ZEPHYR_INCLUDE_BOOT_HEADER_H_ */ diff --git a/boards/nxp/frdm_mcxe31b/doc/frdm_mcxe31b.webp b/boards/nxp/frdm_mcxe31b/doc/frdm_mcxe31b.webp new file mode 100644 index 0000000000000..b1f73e6955e27 Binary files /dev/null and b/boards/nxp/frdm_mcxe31b/doc/frdm_mcxe31b.webp differ diff --git a/boards/nxp/frdm_mcxe31b/doc/index.rst b/boards/nxp/frdm_mcxe31b/doc/index.rst new file mode 100644 index 0000000000000..4271515a14628 --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/doc/index.rst @@ -0,0 +1,176 @@ +.. zephyr:board:: frdm_mcxe31b + +Overview +******** +The FRDM-MCXE31B board is a design and evaluation platform based on the NXP MCXE31B +microcontroller (MCU). NXP MCXE31B MCU based on an Arm Cortex-M7 core, running at +speeds of up to 160 MHz with a 2.97 to 5.5V supply. + +Hardware +******** + +- MCXE31B Arm Cortex-M7 microcontroller running up to 160 MHz +- 4MB dual-bank on chip Flash +- 320KB SRAM + 192KB TCM +- 2x I2C +- 6x SPI +- 16x UART +- On-board MCU-Link debugger with CMSIS-DAP +- Arduino Header, mikroBUS + +For more information about the MCXE31B SoC and FRDM-MCXE31B board, see: + +- `MCXE31X Datasheet`_ +- `MCXE31X Reference Manual`_ +- `FRDM-MCXE31B Board User Manual`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high +bank, from pin 16 to 31. For example, ``PTA2`` is the pin 2 of ``gpioa_l`` (low +bank), and ``PTA20`` is the pin 4 of ``gpioa_h`` (high bank). + +The GPIO controller provides the option to route external input pad interrupts +to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC. +By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller, +unless they are explicity configured to be directed to the WKPU interrupt +controller, as outlined in :zephyr_file:`dts/bindings/gpio/nxp,siul2-gpio.yaml`. + +To find information about which GPIOs are compatible with each interrupt +controller, refer to the device reference manual. + ++-------+-------------+---------------------------+ +| Name | Function | Usage | ++=======+=============+===========================+ +| PTC16 | GPIO | Red LED | ++-------+-------------+---------------------------+ +| PTB22 | GPIO | Green LED | ++-------+-------------+---------------------------+ +| PTC14 | GPIO | Blue LED | ++-------+-------------+---------------------------+ +| PTE3 | LPUART5_RX | UART Console | ++-------+-------------+---------------------------+ +| PTE14 | LPUART5_TX | UART Console | ++-------+-------------+---------------------------+ + +System Clock +============ + +The MCXE31B SoC is configured to use PLL running at 160MHz as a source for +the system clock. + +Serial Port +=========== + +The MCXE31B LPUART5 is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. + +Using LinkServer +---------------- + +Linkserver is the default runner for this board, and supports the factory +default MCU-Link firmware. Follow the instructions in +:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link +firmware. This only needs to be done if the default onboard debug circuit +firmware was changed. To put the board in ``ISP mode`` to program the firmware, +short jumper JP3. + +Using J-Link +------------ + +There are two options. The onboard debug circuit can be updated with Segger +J-Link firmware by following the instructions in +:ref:`mcu-link-jlink-onboard-debug-probe`. +To be able to program the firmware, you need to put the board in ``ISP mode`` +by shorting the jumper JP3. +The second option is to attach a :ref:`jlink-external-debug-probe` to the +10-pin SWD connector (J14) of the board. +For both options use the ``-r jlink`` option with west to use the jlink runner. + +.. code-block:: console + + west flash -r jlink + +Configuring a Console +===================== + +Connect a USB cable from your PC to J13, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxe31b + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 *** + Hello World! frdm_mcxe31b/mcxe31b + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_mcxe31b + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 *** + Hello World! frdm_mcxe31b/mcxe31b + +Troubleshooting +=============== + +.. include:: ../../common/segger-ecc-systemview.rst + :start-after: segger-ecc-systemview + +.. include:: ../../common/board-footer.rst + :start-after: nxp-board-footer + +.. _MCXE31X Datasheet: + https://www.nxp.com/docs/en/data-sheet/MCXEP172M160FB0.pdf + +.. _MCXE31X Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MCXE31XRM&location=null + +.. _FRDM-MCXE31B Board User Manual: + https://www.nxp.com/webapp/Download?colCode=UM12330&location=null&isHTMLorPDF=HTML diff --git a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi new file mode 100644 index 0000000000000..965205033ec69 --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright 2025 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +&pinctrl { + eirq0_default: eirq0_default { + group1 { + pinmux = ; + input-enable; + }; + }; + + pinmux_lpuart_5: pinmux_lpuart_5 { + group1 { + pinmux = ; + output-enable; + }; + + group2 { + pinmux = ; + input-enable; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts new file mode 100644 index 0000000000000..1f98e1de8a734 --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts @@ -0,0 +1,165 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "frdm_mcxe31b-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "NXP FRDM_MCXE31B board"; + compatible = "nxp,mcxe31b"; + + aliases { + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + sw0 = &user_button; + }; + + chosen { + zephyr,sram = &sram; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,flash = &program_flash; + zephyr,flash-controller = &flash; + zephyr,console = &lpuart_5; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpioc_h 0 GPIO_ACTIVE_LOW>; + label = "Red LED"; + }; + + green_led: led_1 { + gpios = <&gpiob_h 6 GPIO_ACTIVE_LOW>; + label = "Green LED"; + }; + + blue_led: led_2 { + gpios = <&gpioc_l 14 GPIO_ACTIVE_LOW>; + label = "Blue LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button_0 { + label = "User SW3"; + gpios = <&gpiod_l 5 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; + +&core0 { + clock-frequency = ; +}; + +&gpiob_h { + status = "okay"; +}; + +&lpuart_5 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart_5>; + pinctrl-names = "default"; + dmas = <&edma 1 44>, <&edma 2 45>; + dma-names = "tx", "rx"; +}; + +&gpioc_l { + status = "okay"; +}; + +&gpioc_h { + status = "okay"; +}; + +&gpiod_l { + status = "okay"; +}; + +&eirq0 { + pinctrl-0 = <&eirq0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&firc { + status = "okay"; + firc-div = "UnDiv"; +}; + +&fxosc { + status = "okay"; + freq = <16000000>; + workmode = "crystal"; + delay = <49>; + overdrive = <12>; +}; + +&pll { + status = "okay"; + workmode = "Integer"; + prediv = <2>; + postdiv = <2>; + multiplier = <120>; + fracloopdiv = <0>; + stepsize = <0>; + stepnum = <0>; + accuracy = "Accuracy9"; + outdiv = <3 3>; +}; + +&mc_cgm { + status = "okay"; + max-ido-change = <50>; + step-duration = <1>; + clk-src-freq = <160000000>; + mux-0-dc-0-div = <1>; + mux-0-dc-1-div = <2>; + mux-0-dc-2-div = <4>; + mux-0-dc-3-div = <2>; + mux-0-dc-4-div = <4>; + mux-0-dc-5-div = <4>; + mux-0-dc-6-div = <1>; +}; diff --git a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.yaml b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.yaml new file mode 100644 index 0000000000000..05752b15a9a5d --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: frdm_mcxe31b +name: NXP FRDM MCXE31B +type: mcu +arch: arm +ram: 288 +flash: 4096 +toolchain: + - zephyr + - gnuarmemb +supported: + - arduino_gpio + - gpio +vendor: nxp diff --git a/boards/nxp/frdm_mcxe31b/frdm_mcxe31b_defconfig b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b_defconfig new file mode 100644 index 0000000000000..de7e80e5ffee4 --- /dev/null +++ b/boards/nxp/frdm_mcxe31b/frdm_mcxe31b_defconfig @@ -0,0 +1,10 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 659c058ef61a0..cf1131fb5d78a 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -40,6 +40,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_AHB clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_APB clock_control_si32_apb.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND clock_control_smartbond.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC clock_control_numaker_scc.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_MC_CGM clock_control_nxp_mc_cgm.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32 clock_control_nxp_s32.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_control_renesas_ra_cgc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_ROOT clock_control_renesas_rx_root_cgc.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index e2c4a071ab09a..2d5ed6198b840 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -86,6 +86,8 @@ source "drivers/clock_control/Kconfig.smartbond" source "drivers/clock_control/Kconfig.numaker" +source "drivers/clock_control/Kconfig.nxp_mc_cgm" + source "drivers/clock_control/Kconfig.nxp_s32" source "drivers/clock_control/Kconfig.agilex5" diff --git a/drivers/clock_control/Kconfig.nxp_mc_cgm b/drivers/clock_control/Kconfig.nxp_mc_cgm new file mode 100644 index 0000000000000..aba3c9b54d9a3 --- /dev/null +++ b/drivers/clock_control/Kconfig.nxp_mc_cgm @@ -0,0 +1,9 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config CLOCK_CONTROL_NXP_MC_CGM + bool "NXP MC_CGM clock driver" + default y + depends on DT_HAS_NXP_MC_CGM_ENABLED + help + Enable support for NXP MC_CGM clock driver. diff --git a/drivers/clock_control/clock_control_nxp_mc_cgm.c b/drivers/clock_control/clock_control_nxp_mc_cgm.c new file mode 100644 index 0000000000000..7cd6b4ff7f7f7 --- /dev/null +++ b/drivers/clock_control/clock_control_nxp_mc_cgm.c @@ -0,0 +1,317 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_mc_cgm + +#include +#include +#include + +#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL +#include +LOG_MODULE_REGISTER(clock_control); + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(fxosc), nxp_fxosc, okay) +const fxosc_config_t fxosc_config = {.freqHz = NXP_FXOSC_FREQ, + .workMode = NXP_FXOSC_WORKMODE, + .startupDelay = NXP_FXOSC_DELAY, + .overdriveProtect = NXP_FXOSC_OVERDRIVE}; +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), nxp_plldig, okay) +const pll_config_t pll_config = { + .workMode = NXP_PLL_WORKMODE, + .preDiv = NXP_PLL_PREDIV, /* PLL input clock predivider: 2 */ + .postDiv = NXP_PLL_POSTDIV, + .multiplier = NXP_PLL_MULTIPLIER, + .fracLoopDiv = NXP_PLL_FRACLOOPDIV, + .stepSize = NXP_PLL_STEPSIZE, + .stepNum = NXP_PLL_STEPNUM, + .accuracy = NXP_PLL_ACCURACY, + .outDiv = NXP_PLL_OUTDIV_POINTER}; +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(mc_cgm), nxp_mc_cgm, okay) +const clock_pcfs_config_t pcfs_config = {.maxAllowableIDDchange = + NXP_PLL_MAXIDOCHANGE, + .stepDuration = NXP_PLL_STEPDURATION, + .clkSrcFreq = NXP_PLL_CLKSRCFREQ}; +#endif + +static int mc_cgm_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) +{ +#if defined(CONFIG_CAN_MCUX_FLEXCAN) + switch ((uint32_t)sub_system) { + case MCUX_FLEXCAN0_CLK: + CLOCK_EnableClock(kCLOCK_Flexcan0); + break; + case MCUX_FLEXCAN1_CLK: + CLOCK_EnableClock(kCLOCK_Flexcan1); + break; + case MCUX_FLEXCAN2_CLK: + CLOCK_EnableClock(kCLOCK_Flexcan2); + break; + case MCUX_FLEXCAN3_CLK: + CLOCK_EnableClock(kCLOCK_Flexcan3); + break; + case MCUX_FLEXCAN4_CLK: + CLOCK_EnableClock(kCLOCK_Flexcan4); + break; + case MCUX_FLEXCAN5_CLK: + CLOCK_EnableClock(kCLOCK_Flexcan5); + break; + default: + break; + } +#endif /* defined(CONFIG_CAN_MCUX_MCAN) */ + +#if defined(CONFIG_UART_MCUX_LPUART) + switch ((uint32_t)sub_system) { + case MCUX_LPUART0_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart0); + break; + case MCUX_LPUART1_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart1); + break; + case MCUX_LPUART2_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart2); + break; + case MCUX_LPUART3_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart3); + break; + case MCUX_LPUART4_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart4); + break; + case MCUX_LPUART5_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart5); + break; + case MCUX_LPUART6_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart6); + break; + case MCUX_LPUART7_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart7); + break; + case MCUX_LPUART8_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart8); + break; + case MCUX_LPUART9_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart9); + break; + case MCUX_LPUART10_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart10); + break; + case MCUX_LPUART11_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart11); + break; + case MCUX_LPUART12_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart12); + break; + case MCUX_LPUART13_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart13); + break; + case MCUX_LPUART14_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart14); + break; + case MCUX_LPUART15_CLK: + CLOCK_EnableClock(kCLOCK_Lpuart15); + break; + default: + break; + } +#endif /* defined(CONFIG_UART_MCUX_LPUART) */ + +#if defined(CONFIG_SPI_NXP_LPSPI) + switch ((uint32_t)sub_system) { + case MCUX_LPSPI0_CLK: + CLOCK_EnableClock(kCLOCK_Lpspi0); + break; + case MCUX_LPSPI1_CLK: + CLOCK_EnableClock(kCLOCK_Lpspi1); + break; + case MCUX_LPSPI2_CLK: + CLOCK_EnableClock(kCLOCK_Lpspi2); + break; + case MCUX_LPSPI3_CLK: + CLOCK_EnableClock(kCLOCK_Lpspi3); + break; + case MCUX_LPSPI4_CLK: + CLOCK_EnableClock(kCLOCK_Lpspi4); + break; + case MCUX_LPSPI5_CLK: + CLOCK_EnableClock(kCLOCK_Lpspi5); + break; + default: + break; + } +#endif /* defined(CONFIG_SPI_NXP_LPSPI) */ + +#if defined(CONFIG_I2C_MCUX_LPI2C) + switch ((uint32_t)sub_system) { + case MCUX_LPI2C0_CLK: + CLOCK_EnableClock(kCLOCK_Lpi2c0); + break; + case MCUX_LPI2C1_CLK: + CLOCK_EnableClock(kCLOCK_Lpi2c1); + break; + default: + break; + } +#endif /* defined(CONFIG_I2C_MCUX_LPI2C) */ + + return 0; +} + +static int mc_cgm_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system) +{ + return 0; +} + +static int mc_cgm_get_subsys_rate(const struct device *dev, clock_control_subsys_t sub_system, + uint32_t *rate) +{ + uint32_t clock_name = (uint32_t)sub_system; + + switch (clock_name) { +#if defined(CONFIG_UART_MCUX_LPUART) + case MCUX_LPUART0_CLK: + case MCUX_LPUART8_CLK: + *rate = CLOCK_GetAipsPlatClkFreq(); + break; + case MCUX_LPUART1_CLK: + case MCUX_LPUART2_CLK: + case MCUX_LPUART3_CLK: + case MCUX_LPUART4_CLK: + case MCUX_LPUART5_CLK: + case MCUX_LPUART6_CLK: + case MCUX_LPUART7_CLK: + case MCUX_LPUART9_CLK: + case MCUX_LPUART10_CLK: + case MCUX_LPUART11_CLK: + case MCUX_LPUART12_CLK: + case MCUX_LPUART13_CLK: + case MCUX_LPUART14_CLK: + case MCUX_LPUART15_CLK: + *rate = CLOCK_GetAipsSlowClkFreq(); + break; +#endif /* defined(CONFIG_UART_MCUX_LPUART) */ + +#if defined(CONFIG_SPI_NXP_LPSPI) + case MCUX_LPSPI0_CLK: + *rate = CLOCK_GetAipsPlatClkFreq(); + break; + case MCUX_LPSPI1_CLK: + case MCUX_LPSPI2_CLK: + case MCUX_LPSPI3_CLK: + case MCUX_LPSPI4_CLK: + case MCUX_LPSPI5_CLK: + *rate = CLOCK_GetAipsSlowClkFreq(); + break; +#endif /* defined(CONFIG_SPI_NXP_LPSPI) */ + +#if defined(CONFIG_I2C_MCUX_LPI2C) + case MCUX_LPI2C0_CLK: + case MCUX_LPI2C1_CLK: + *rate = CLOCK_GetAipsSlowClkFreq(); + break; +#endif /* defined(CONFIG_I2C_MCUX_LPI2C) */ + +#if defined(CONFIG_CAN_MCUX_FLEXCAN) + case MCUX_FLEXCAN0_CLK: + *rate = CLOCK_GetFlexcanPeClkFreq(0); + break; + case MCUX_FLEXCAN1_CLK: + *rate = CLOCK_GetFlexcanPeClkFreq(1); + break; + case MCUX_FLEXCAN2_CLK: + *rate = CLOCK_GetFlexcanPeClkFreq(2); + break; + case MCUX_FLEXCAN3_CLK: + *rate = CLOCK_GetFlexcanPeClkFreq(3); + break; + case MCUX_FLEXCAN4_CLK: + *rate = CLOCK_GetFlexcanPeClkFreq(4); + break; + case MCUX_FLEXCAN5_CLK: + *rate = CLOCK_GetFlexcanPeClkFreq(5); + break; +#endif /* defined(CONFIG_CAN_MCUX_FLEXCAN) */ + } + return 0; +} + +static int mc_cgm_init(const struct device *dev) +{ +#if defined(FSL_FEATURE_PMC_HAS_LAST_MILE_REGULATOR) && (FSL_FEATURE_PMC_HAS_LAST_MILE_REGULATOR) + /* Enables PMC last mile regulator before enable PLL. */ + if ((PMC->LVSC & PMC_LVSC_LVD15S_MASK) != 0U) { + /* External bipolar junction transistor is connected between external voltage and + * V15 input pin. + */ + PMC->CONFIG |= PMC_CONFIG_LMBCTLEN_MASK; + } + while ((PMC->LVSC & PMC_LVSC_LVD15S_MASK) != 0U) { + } + PMC->CONFIG |= PMC_CONFIG_LMEN_MASK; + while ((PMC->CONFIG & PMC_CONFIG_LMSTAT_MASK) == 0u) { + } +#endif /* FSL_FEATURE_PMC_HAS_LAST_MILE_REGULATOR */ + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(firc), nxp_firc, okay) + /* Switch the FIRC_DIV_SEL to the desired diveder. */ + CLOCK_SetFircDiv(NXP_FIRC_DIV); + /* Disable FIRC in standby mode. */ + CLOCK_DisableFircInStandbyMode(); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(sirc), nxp_sirc, okay) + /* Disable SIRC in standby mode. */ + CLOCK_DisableSircInStandbyMode(); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(fxosc), nxp_fxosc, okay) + /* Enable FXOSC. */ + CLOCK_InitFxosc(&fxosc_config); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), nxp_plldig, okay) + /* Enable PLL. */ + CLOCK_InitPll(&pll_config); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(mc_cgm), nxp_mc_cgm, okay) + CLOCK_SelectSafeClock(kFIRC_CLK_to_MUX0); + /* Configure MUX_0_CSC dividers */ + CLOCK_SetClkMux0DivTriggerType(KCLOCK_CommonTriggerUpdate); + CLOCK_SetClkDiv(kCLOCK_DivCoreClk, NXP_PLL_MUX_0_DC_0_DIV); + CLOCK_SetClkDiv(kCLOCK_DivAipsPlatClk, NXP_PLL_MUX_0_DC_1_DIV); + CLOCK_SetClkDiv(kCLOCK_DivAipsSlowClk, NXP_PLL_MUX_0_DC_2_DIV); + CLOCK_SetClkDiv(kCLOCK_DivHseClk, NXP_PLL_MUX_0_DC_3_DIV); + CLOCK_SetClkDiv(kCLOCK_DivDcmClk, NXP_PLL_MUX_0_DC_4_DIV); +#ifdef MC_CGM_MUX_0_DC_5_DIV_MASK + CLOCK_SetClkDiv(kCLOCK_DivLbistClk, NXP_PLL_MUX_0_DC_5_DIV); +#endif +#ifdef MC_CGM_MUX_0_DC_6_DIV_MASK + CLOCK_SetClkDiv(kCLOCK_DivQspiClk, NXP_PLL_MUX_0_DC_6_DIV); +#endif + CLOCK_CommonTriggerClkMux0DivUpdate(); + CLOCK_ProgressiveClockFrequencySwitch(kPLL_PHI0_CLK_to_MUX0, + &pcfs_config); +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClockUpdate(); + + return 0; +} + +static DEVICE_API(clock_control, mcux_mcxe31x_clock_api) = { + .on = mc_cgm_clock_control_on, + .off = mc_cgm_clock_control_off, + .get_rate = mc_cgm_get_subsys_rate, +}; + +DEVICE_DT_INST_DEFINE(0, mc_cgm_init, NULL, NULL, NULL, PRE_KERNEL_1, + CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &mcux_mcxe31x_clock_api); diff --git a/drivers/interrupt_controller/Kconfig.nxp_siul2 b/drivers/interrupt_controller/Kconfig.nxp_siul2 index ba439cd5d60cf..ae2c64f261c51 100644 --- a/drivers/interrupt_controller/Kconfig.nxp_siul2 +++ b/drivers/interrupt_controller/Kconfig.nxp_siul2 @@ -15,7 +15,7 @@ if NXP_SIUL2_EIRQ config NXP_SIUL2_EIRQ_EXT_INTERRUPTS_MAX int default 8 if SOC_SERIES_S32ZE - default 32 if SOC_SERIES_S32K3 + default 32 if SOC_SERIES_S32K3 || SOC_SERIES_MCXE31X help Number of SIUL2 external interrupts per controller. This is a SoC integration option. diff --git a/drivers/interrupt_controller/intc_nxp_siul2_eirq.c b/drivers/interrupt_controller/intc_nxp_siul2_eirq.c index 27cc145e877b0..8668925d9beef 100644 --- a/drivers/interrupt_controller/intc_nxp_siul2_eirq.c +++ b/drivers/interrupt_controller/intc_nxp_siul2_eirq.c @@ -28,13 +28,20 @@ #define SIUL2_IFER0 0x28 /* SIUL2 Interrupt Filter Maximum Counter Register */ #define SIUL2_IFMCR(n) (0x30 + 0x4 * (n)) +#ifndef SIUL2_IFMCR_MAXCNT_MASK #define SIUL2_IFMCR_MAXCNT_MASK GENMASK(3, 0) +#endif +#ifndef SIUL2_IFMCR_MAXCNT #define SIUL2_IFMCR_MAXCNT(v) FIELD_PREP(SIUL2_IFMCR_MAXCNT_MASK, (v)) +#endif /* SIUL2 Interrupt Filter Clock Prescaler Register */ #define SIUL2_IFCPR 0xb0 +#ifndef SIUL2_IFCPR_IFCP_MASK #define SIUL2_IFCPR_IFCP_MASK GENMASK(3, 0) +#endif +#ifndef SIUL2_IFCPR_IFCP #define SIUL2_IFCPR_IFCP(v) FIELD_PREP(SIUL2_IFCPR_IFCP_MASK, (v)) - +#endif /* Handy accessors */ #define REG_READ(r) sys_read32(config->base + (r)) #define REG_WRITE(r, v) sys_write32((v), config->base + (r)) diff --git a/drivers/pinctrl/Kconfig.nxp_siul2 b/drivers/pinctrl/Kconfig.nxp_siul2 index e60391fa8445a..64cb16053ca7c 100644 --- a/drivers/pinctrl/Kconfig.nxp_siul2 +++ b/drivers/pinctrl/Kconfig.nxp_siul2 @@ -4,6 +4,7 @@ config PINCTRL_NXP_SIUL2 bool "Pin controller driver for NXP SIUL2" default y - depends on DT_HAS_NXP_S32ZE_SIUL2_PINCTRL_ENABLED || DT_HAS_NXP_S32K3_SIUL2_PINCTRL_ENABLED + depends on DT_HAS_NXP_S32ZE_SIUL2_PINCTRL_ENABLED || DT_HAS_NXP_S32K3_SIUL2_PINCTRL_ENABLED || \ + DT_HAS_NXP_MCXE31X_SIUL2_PINCTRL_ENABLED help Enable pin controller driver for NXP SIUL2. diff --git a/dts/arm/nxp/nxp_mcxe31b.dtsi b/dts/arm/nxp/nxp_mcxe31b.dtsi new file mode 100644 index 0000000000000..ba7fec4f3b4d0 --- /dev/null +++ b/dts/arm/nxp/nxp_mcxe31b.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + itcm: memory@0 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x0 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + itcm1: memory@11400000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x11400000 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM1"; + }; + + dtcm: memory@20000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(64)>; + zephyr,memory-region = "DTCM"; + }; + + /* stdby_ram memory supports content retention in Standby mode */ + stdby_ram: memory@20400000 { + compatible = "mmio-sram"; + reg = <0x20400000 DT_SIZE_K(32)>; + }; + + /* sram memory is available only in Run mode */ + sram: memory@20408000 { + compatible = "mmio-sram"; + reg = <0x20408000 DT_SIZE_K(288)>; + }; + + dtcm1: memory@21400000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21400000 DT_SIZE_K(64)>; + zephyr,memory-region = "DTCM1"; + }; + + peripheral: peripheral@40000000 { + ranges = <0x0 0x40000000 0x10000000>; + }; + }; +}; + +#include diff --git a/dts/arm/nxp/nxp_mcxe31x_common.dtsi b/dts/arm/nxp/nxp_mcxe31x_common.dtsi new file mode 100644 index 0000000000000..5b1c6e348b545 --- /dev/null +++ b/dts/arm/nxp/nxp_mcxe31x_common.dtsi @@ -0,0 +1,1061 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <0x1>; + #size-cells = <0>; + core0: cpu@0 { + reg = <0>; + device_type = "cpu"; + compatible = "arm,cortex-m7"; + }; + }; + + /* Dummy pinctrl node, filled with pin mux options at board level */ + pinctrl: pinctrl { + compatible = "nxp,mcxe31x-siul2-pinctrl"; + status = "okay"; + }; +}; + +&peripheral { + #address-cells = <1>; + #size-cells = <1>; + adc_0: adc@a0000 { + compatible = "nxp,adc"; + reg = <0xa0000 0x3d4>; + interrupts = <180 0>; + status = "disabled"; + }; + + adc_1: adc@a4000 { + compatible = "nxp,adc"; + reg = <0xa4000 0x3d4>; + interrupts = <181 0>; + status = "disabled"; + }; + + adc_2: adc@a8000 { + compatible = "nxp,adc"; + reg = <0xa8000 0x3d4>; + interrupts = <182 0>; + status = "disabled"; + }; + + axbs_lite: axbs@200000 { + compatible = "nxp,axbs"; + reg = <0x200000 0x630>; + status = "disabled"; + }; + + bctu: bctu@84000 { + compatible = "nxp,bctu"; + reg = <0x84000 0x490>; + status = "disabled"; + }; + + cmu_0: cmu-fc@2bc000 { + compatible = "nxp,cmu-fc"; + reg = <0x2bc000 0x34>; + status = "disabled"; + }; + + cmu_1: cmu-fm@2bc020 { + compatible = "nxp,cmu-fm"; + reg = <0x2bc020 0x2c>; + status = "disabled"; + }; + + cmu_2: cmu-fm@2bc040 { + compatible = "nxp,cmu-fm"; + reg = <0x2bc040 0x2c>; + status = "disabled"; + }; + + cmu_3: cmu-fc@2bc060 { + compatible = "nxp,cmu-fc"; + reg = <0x2bc060 0x34>; + status = "disabled"; + }; + + cmu_4: cmu-fc@2bc080 { + compatible = "nxp,cmu-fc"; + reg = <0x2bc080 0x34>; + status = "disabled"; + }; + + cmu_5: cmu-fc@2bc0a0 { + compatible = "nxp,cmu-fc"; + reg = <0x2bc0a0 0x34>; + status = "disabled"; + }; + + configuration: configuration@39c000 { + compatible = "nxp,configuration"; + reg = <0x39c000 0x84>; + status = "disabled"; + }; + + crc: crc@380000 { + compatible = "nxp,crc"; + reg = <0x380000 0x28>; + }; + + dcm: dcm@2ac000 { + compatible = "nxp,dcm"; + reg = <0x2ac000 0xa0>; + status = "disabled"; + }; + + dcm_gpr: dcm-gpr@2ac200 { + compatible = "nxp,dcm-gpr"; + reg = <0x2ac200 0x510>; + status = "disabled"; + }; + + dmamux_0: dmamux@280000 { + compatible = "nxp,dmamux"; + reg = <0x280000 0x17>; + status = "disabled"; + }; + + dmamux_1: dmamux@284000 { + compatible = "nxp,dmamux"; + reg = <0x284000 0x17>; + status = "disabled"; + }; + + edma: edma@20c000 { + #dma-cells = <2>; + compatible = "nxp,mcux-edma"; + reg = <0x20c000 0x19c>; + dma-channels = <32>; + dma-requests = <128>; + interrupts = <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>, + <12 0>, <13 0>, <14 0>, <15 0>, + <16 0>, <17 0>, <18 0>, <19 0>, + <20 0>, <21 0>, <22 0>, <23 0>, + <24 0>, <25 0>, <26 0>, <27 0>, + <28 0>, <29 0>, <30 0>, <31 0>, + <32 0>, <33 0>, <34 0>, <35 0>; + status = "disabled"; + }; + + eim: eim@258000 { + compatible = "nxp,eim"; + reg = <0x258000 0x8a4>; + status = "disabled"; + }; + + emac: emac@480000 { + compatible = "nxp,emac"; + reg = <0x480000 0x120c>; + interrupts = <105 0>; + status = "disabled"; + }; + + emios_0: emios@88000 { + compatible = "nxp,emios"; + reg = <0x88000 0x338>; + interrupts = <61 0>, <62 0>, <63 0>, <64 0>, + <65 0>, <66 0>; + interrupt-names = "emios0-2", "emios0-3", "emios0-4", + "emios0-5", "emios0-6", "emios0-7"; + status = "disabled"; + }; + + emios_1: emios@8c000 { + compatible = "nxp,emios"; + reg = <0x8c000 0x338>; + status = "disabled"; + }; + + emios_2: emios@90000 { + compatible = "nxp,emios"; + reg = <0x90000 0x338>; + status = "disabled"; + }; + + erm: erm@25c000 { + compatible = "nxp,erm"; + reg = <0x25c000 0x258>; + interrupts = <36 0>, <37 0>; + interrupt-names = "erm-0", "erm-1"; + status = "disabled"; + }; + + fccu: fccu@384000 { + compatible = "nxp,fccu"; + reg = <0x384000 0x158>; + status = "disabled"; + }; + + firc: firc@2d0000 { + compatible = "nxp,firc"; + reg = <0x2d0000 0x28>; + status = "disabled"; + }; + + flash: flash-c40@2ec000 { + compatible = "nxp,pflash"; + reg = <0x2ec000 0x19c>; + interrupts = <48 0>, <49 0>, <50 0>; + interrupt-names = "flash-0", "flash-1", "flash-2"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + program_flash: memory@400000 { + compatible = "soc-nv-flash"; + reg = <0x400000 DT_SIZE_K(4096)>; + }; + + }; + + flexcan_0: flexcan@304000 { + compatible = "nxp,flexcan"; + reg = <0x304000 0x321c>; + interrupts = <109 0>, <110 0>, <111 0>, <112 0>; + interrupt-names = "flexcan0-0", "flexcan0-1", "flexcan0-2", "flexcan0-3"; + clocks = <&mc_cgm MCUX_FLEXCAN0_CLK>; + clk-source = <0>; + status = "disabled"; + }; + + flexcan_1: flexcan@308000 { + compatible = "nxp,flexcan"; + reg = <0x308000 0xd4c>; + interrupts = <113 0>, <114 0>, <115 0>; + interrupt-names = "flexcan1-0", "flexcan1-1", "flexcan1-2"; + clocks = <&mc_cgm MCUX_FLEXCAN1_CLK>; + clk-source = <0>; + status = "disabled"; + }; + + flexcan_2: flexcan@30c000 { + compatible = "nxp,flexcan"; + reg = <0x30c000 0xd4c>; + interrupts = <116 0>, <117 0>, <118 0>; + interrupt-names = "flexcan2-0", "flexcan2-1", "flexcan2-2"; + clocks = <&mc_cgm MCUX_FLEXCAN2_CLK>; + clk-source = <0>; + status = "disabled"; + }; + + flexcan_3: flexcan@310000 { + compatible = "nxp,flexcan"; + reg = <0x310000 0xccc>; + interrupts = <119 0>, <120 0>; + interrupt-names = "flexcan3-0", "flexcan3-1"; + clocks = <&mc_cgm MCUX_FLEXCAN3_CLK>; + clk-source = <0>; + status = "disabled"; + }; + + flexcan_4: flexcan@314000 { + compatible = "nxp,flexcan"; + reg = <0x314000 0xccc>; + interrupts = <121 0>, <122 0>; + interrupt-names = "flexcan4-0", "flexcan4-1"; + clocks = <&mc_cgm MCUX_FLEXCAN4_CLK>; + clk-source = <0>; + status = "disabled"; + }; + + flexcan_5: flexcan@318000 { + compatible = "nxp,flexcan"; + reg = <0x318000 0xccc>; + interrupts = <123 0>, <124 0>; + interrupt-names = "flexcan5-0", "flexcan5-1"; + clocks = <&mc_cgm MCUX_FLEXCAN5_CLK>; + clk-source = <0>; + status = "disabled"; + }; + + flexio: flexio@324000 { + compatible = "nxp,flexio"; + reg = <0x324000 0x93c>; + interrupts = <139 0>; + clocks = <&mc_cgm MCUX_FLEXIO_CLK>; + status = "disabled"; + }; + + fxosc: fxosc@2d4000 { + compatible = "nxp,fxosc"; + reg = <0x2d4000 0x24>; + status = "disabled"; + }; + + intm: intm@27c000 { + compatible = "nxp,intm"; + reg = <0x27c000 0x64>; + status = "disabled"; + }; + + jdc: jdc@394000 { + compatible = "nxp,jdc"; + reg = <0x394000 0x2c>; + status = "disabled"; + }; + + lcu_0: lcu@98000 { + compatible = "nxp,lcu"; + reg = <0x98000 0x2c8>; + interrupts = <92 0>; + status = "disabled"; + }; + + lcu_1: lcu@9c000 { + compatible = "nxp,lcu"; + reg = <0x9c000 0x2c8>; + interrupts = <93 0>; + status = "disabled"; + }; + + lpcmp_0: lpcmp@370000 { + compatible = "nxp,lpcmp"; + reg = <0x370000 0x50>; + interrupts = <183 0>; + status = "disabled"; + }; + + lpcmp_1: lpcmp@374000 { + compatible = "nxp,lpcmp"; + reg = <0x374000 0x50>; + interrupts = <184 0>; + status = "disabled"; + }; + + lpcmp_2: lpcmp@4e8000 { + compatible = "nxp,lpcmp"; + reg = <0x4e8000 0x50>; + interrupts = <185 0>; + status = "disabled"; + }; + + lpi2c_0: lpi2c@350000 { + compatible = "nxp,lpi2c"; + reg = <0x350000 0x190>; + interrupts = <161 0>; + clocks = <&mc_cgm MCUX_LPI2C0_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpi2c_1: lpi2c@354000 { + compatible = "nxp,lpi2c"; + reg = <0x354000 0x190>; + interrupts = <162 0>; + clocks = <&mc_cgm MCUX_LPI2C1_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpspi_0: lpspi@358000 { + compatible = "nxp,lpspi"; + reg = <0x358000 0x81c>; + interrupts = <165 0>; + clocks = <&mc_cgm MCUX_LPSPI0_CLK>; + rx-fifo-size = <4>; + tx-fifo-size = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpspi_1: lpspi@35c000 { + compatible = "nxp,lpspi"; + reg = <0x35c000 0x81c>; + interrupts = <166 0>; + clocks = <&mc_cgm MCUX_LPSPI1_CLK>; + rx-fifo-size = <4>; + tx-fifo-size = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpspi_2: lpspi@360000 { + compatible = "nxp,lpspi"; + reg = <0x360000 0x81c>; + interrupts = <167 0>; + clocks = <&mc_cgm MCUX_LPSPI2_CLK>; + rx-fifo-size = <4>; + tx-fifo-size = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpspi_3: lpspi@364000 { + compatible = "nxp,lpspi"; + reg = <0x364000 0x81c>; + interrupts = <168 0>; + clocks = <&mc_cgm MCUX_LPSPI3_CLK>; + rx-fifo-size = <4>; + tx-fifo-size = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpspi_4: lpspi@4bc000 { + compatible = "nxp,lpspi"; + reg = <0x4bc000 0x81c>; + interrupts = <169 0>; + clocks = <&mc_cgm MCUX_LPSPI4_CLK>; + rx-fifo-size = <4>; + tx-fifo-size = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpspi_5: lpspi@4c0000 { + compatible = "nxp,lpspi"; + reg = <0x4c0000 0x81c>; + interrupts = <170 0>; + clocks = <&mc_cgm MCUX_LPSPI5_CLK>; + rx-fifo-size = <4>; + tx-fifo-size = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpuart_0: lpuart@328000 { + compatible = "nxp,lpuart"; + reg = <0x328000 0x50>; + interrupts = <141 0>; + clocks = <&mc_cgm MCUX_LPUART0_CLK>; + status = "disabled"; + }; + + lpuart_1: lpuart@32c000 { + compatible = "nxp,lpuart"; + reg = <0x32c000 0x50>; + interrupts = <142 0>; + clocks = <&mc_cgm MCUX_LPUART1_CLK>; + status = "disabled"; + }; + + lpuart_2: lpuart@330000 { + compatible = "nxp,lpuart"; + reg = <0x330000 0x50>; + interrupts = <143 0>; + clocks = <&mc_cgm MCUX_LPUART2_CLK>; + status = "disabled"; + }; + + lpuart_3: lpuart@334000 { + compatible = "nxp,lpuart"; + reg = <0x334000 0x50>; + interrupts = <144 0>; + clocks = <&mc_cgm MCUX_LPUART3_CLK>; + status = "disabled"; + }; + + lpuart_4: lpuart@338000 { + compatible = "nxp,lpuart"; + reg = <0x338000 0x50>; + interrupts = <145 0>; + clocks = <&mc_cgm MCUX_LPUART4_CLK>; + status = "disabled"; + }; + + lpuart_5: lpuart@33c000 { + compatible = "nxp,lpuart"; + reg = <0x33c000 0x50>; + interrupts = <146 0>; + clocks = <&mc_cgm MCUX_LPUART5_CLK>; + status = "disabled"; + }; + + lpuart_6: lpuart@340000 { + compatible = "nxp,lpuart"; + reg = <0x340000 0x50>; + interrupts = <147 0>; + clocks = <&mc_cgm MCUX_LPUART6_CLK>; + status = "disabled"; + }; + + lpuart_7: lpuart@344000 { + compatible = "nxp,lpuart"; + reg = <0x344000 0x50>; + interrupts = <148 0>; + clocks = <&mc_cgm MCUX_LPUART7_CLK>; + status = "disabled"; + }; + + lpuart_8: lpuart@48c000 { + compatible = "nxp,lpuart"; + reg = <0x48c000 0x50>; + interrupts = <149 0>; + clocks = <&mc_cgm MCUX_LPUART8_CLK>; + status = "disabled"; + }; + + lpuart_9: lpuart@490000 { + compatible = "nxp,lpuart"; + reg = <0x490000 0x50>; + interrupts = <150 0>; + clocks = <&mc_cgm MCUX_LPUART9_CLK>; + status = "disabled"; + }; + + lpuart_10: lpuart@494000 { + compatible = "nxp,lpuart"; + reg = <0x494000 0x50>; + interrupts = <151 0>; + clocks = <&mc_cgm MCUX_LPUART10_CLK>; + status = "disabled"; + }; + + lpuart_11: lpuart@498000 { + compatible = "nxp,lpuart"; + reg = <0x498000 0x50>; + interrupts = <152 0>; + clocks = <&mc_cgm MCUX_LPUART11_CLK>; + status = "disabled"; + }; + + lpuart_12: lpuart@49c000 { + compatible = "nxp,lpuart"; + reg = <0x49c000 0x50>; + interrupts = <153 0>; + clocks = <&mc_cgm MCUX_LPUART12_CLK>; + status = "disabled"; + }; + + lpuart_13: lpuart@4a0000 { + compatible = "nxp,lpuart"; + reg = <0x4a0000 0x50>; + interrupts = <154 0>; + clocks = <&mc_cgm MCUX_LPUART13_CLK>; + status = "disabled"; + }; + + lpuart_14: lpuart@4a4000 { + compatible = "nxp,lpuart"; + reg = <0x4a4000 0x50>; + interrupts = <155 0>; + clocks = <&mc_cgm MCUX_LPUART14_CLK>; + status = "disabled"; + }; + + lpuart_15: lpuart@4a8000 { + compatible = "nxp,lpuart"; + reg = <0x4a8000 0x50>; + interrupts = <156 0>; + clocks = <&mc_cgm MCUX_LPUART15_CLK>; + status = "disabled"; + }; + + mc_cgm: mc_cgm@2d8000 { + compatible = "nxp,mc-cgm"; + reg = <0x2d8000 0x61c>; + #clock-cells = <1>; + status = "disabled"; + }; + + mc_me: mc-me@2dc000 { + compatible = "nxp,mc-me"; + reg = <0x2dc000 0x554>; + status = "disabled"; + }; + + mc_rgm: mc-rgm@28c000 { + compatible = "nxp,mc-rgm"; + reg = <0x28c000 0x4c>; + status = "disabled"; + }; + + mcm_0: mcm@e0080000 { + compatible = "nxp,mcm"; + reg = <0xe0080000 0x430>; + status = "disabled"; + }; + + mdm_ap: mdm-ap@250600 { + compatible = "nxp,mdm-ap"; + reg = <0x250600 0x11c>; + status = "disabled"; + }; + + mscm: mscm@260000 { + compatible = "nxp,mscm"; + reg = <0x260000 0xa6e>; + status = "disabled"; + }; + + mu0_b: mu@38c000 { + compatible = "nxp,mu"; + reg = <0x38c000 0x2ac>; + status = "disabled"; + }; + + mu1_b: mu@4ec000 { + compatible = "nxp,mu"; + reg = <0x4ec000 0x2ac>; + }; + + pflash: pflash@268000 { + compatible = "nxp,pflash"; + reg = <0x268000 0x4dc>; + status = "disabled"; + }; + + pit_0: pit@b0000 { + compatible = "nxp,pit"; + reg = <0xb0000 0x15c>; + interrupts = <96 0>; + clocks = <&mc_cgm MCUX_PIT0_CLK>; + max-load-value = <0xffffffff>; + status = "disabled"; + }; + + pit_1: pit@b4000 { + compatible = "nxp,pit"; + reg = <0xb4000 0x15c>; + interrupts = <97 0>; + clocks = <&mc_cgm MCUX_PIT1_CLK>; + max-load-value = <0xffffffff>; + status = "disabled"; + }; + + pit_2: pit@2fc000 { + compatible = "nxp,pit"; + reg = <0x2fc000 0x15c>; + interrupts = <98 0>; + clocks = <&mc_cgm MCUX_PIT2_CLK>; + max-load-value = <0xffffffff>; + status = "disabled"; + }; + + pll: plldig@402e0000 { + compatible = "nxp,plldig"; + reg = <0x402e0000 0xa4>; + status = "disabled"; + }; + + pmc: pmc@2e8000 { + compatible = "nxp,pmc"; + reg = <0x2e8000 0x2c>; + interrupts = <52 0>; + status = "disabled"; + }; + + pramc_0: pramc@264000 { + compatible = "nxp,pramc"; + reg = <0x264000 0x20>; + status = "disabled"; + }; + + pramc_1: pramc@464000 { + compatible = "nxp,pramc"; + reg = <0x464000 0x20>; + status = "disabled"; + }; + + quadspi: qspi@4cc000 { + compatible = "nxp,qspi"; + reg = <0x4cc000 0x37c>; + interrupts = <173 0>; + status = "disabled"; + }; + + quadspi_ardb: @68000000 { + compatible = "nxp,"; + reg = <0x68000000 0x21c>; + status = "disabled"; + }; + + rtc: rtc@288000 { + compatible = "nxp,rtc"; + reg = <0x288000 0x34>; + interrupts = <102 0>; + status = "disabled"; + }; + + sai_0: sai@36c000 { + compatible = "nxp,sai"; + reg = <0x36c000 0x100>; + interrupts = <174 0>; + status = "disabled"; + }; + + sai_1: sai@4dc000 { + compatible = "nxp,sai"; + reg = <0x4dc000 0x100>; + interrupts = <175 0>; + status = "disabled"; + }; + + sda_ap: sda-ap@254700 { + compatible = "nxp,sda-ap"; + reg = <0x254700 0x11c>; + status = "disabled"; + }; + + selftest: selftest-gpr@3b0000 { + compatible = "nxp,selftest-gpr"; + reg = <0x3b0000 0x34>; + status = "disabled"; + }; + + sema42: sema42@460000 { + compatible = "nxp,sema42"; + reg = <0x460000 0x52>; + status = "disabled"; + }; + + sirc: sirc@402c8000 { + compatible = "nxp,sirc"; + reg = <0x402c8000 0x2c>; + status = "disabled"; + }; + + siul2_0: siul2@290000 { + reg = <0x290000 0x17d4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x290000 0x17d4>; + + eirq0: eirq@10 { + compatible = "nxp,siul2-eirq"; + reg = <0x10 0xb4>; + #address-cells = <0>; + interrupts = <53 0>, <54 0>, <55 0>, <56 0>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpioa_l: gpio@1702 { + compatible = "nxp,siul2-gpio"; + reg = <0x1702 0x02>, <0x240 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 0>, <1 1>, <2 2>, <3 3>, <4 4>, + <5 5>, <6 6>, <7 7>, <8 16>, <9 17>, + <10 18>, <11 19>, <12 20>, <13 21>, + <14 22>, <15 23>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <1 9>, <2 4>, <6 19>, + <8 27>, <9 25>, <13 8>, <15 24>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpioa_h: gpio@1700 { + compatible = "nxp,siul2-gpio"; + reg = <0x1700 0x02>, <0x280 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 4>, <2 0>, <3 1>, <4 2>, + <5 3>, <9 5>, <12 6>, <14 7>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <0 35>, <4 63>, <9 38>, + <10 39>, <14 41>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpiob_l: gpio@1706 { + compatible = "nxp,siul2-gpio"; + reg = <0x1706 0x02>, <0x2c0 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>, + <5 13>, <8 14>, <9 15>, <10 24>, <11 25>, + <12 26>, <13 27>, <14 28>, <15 29>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <0 11>, <2 12>, <8 29>, + <9 21>, <11 20>, <12 16>, <13 15>, <15 37>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + gpio-reserved-ranges = <6 2>; + status = "disabled"; + }; + + gpiob_h: gpio@1704 { + compatible = "nxp,siul2-gpio"; + reg = <0x1704 0x02>, <0x300 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 30>, <1 31>, <5 8>, <6 9>, <7 10>, + <8 11>, <9 12>, <10 13>, <12 14>, <15 15>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <0 17>, <1 18>, <3 42>, + <5 43>, <7 44>, <10 45>, <12 46>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpioc_l: gpio@170a { + compatible = "nxp,siul2-gpio"; + reg = <0x170a 0x02>, <0x340 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 1>, <1 1>, <2 2>, <3 3>, <4 4>, + <5 5>, <6 6>, <7 7>, <8 16>, <9 17>, + <10 18>, <11 19>, <12 20>, <13 21>, + <14 22>, <15 23>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <6 7>, <7 6>, <9 14>, <11 22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpioc_h: gpio@1708 { + compatible = "nxp,siul2-gpio"; + reg = <0x1708 0x02>, <0x380 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <4 16>, <5 17>, <7 18>, <8 19>, + <9 20>, <10 21>, <11 22>, <13 23>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <2 40>, <4 47>, <7 48>, + <8 50>, <9 49>, <10 52>, <13 51>, <15 53>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpiod_l: gpio@170e { + compatible = "nxp,siul2-gpio"; + reg = <0x170e 0x02>, <0x3c0 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>, + <5 13>, <6 14>, <7 15>, <8 24>, + <9 25>, <10 26>, <11 27>, <12 28>, + <13 29>, <14 30>, <15 31>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <0 10>, <2 13>, <3 5>, + <4 26>, <13 28>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpiod_h: gpio@170c { + compatible = "nxp,siul2-gpio"; + reg = <0x170c 0x02>, <0x400 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <1 24>, <4 25>, <5 26>, <6 27>, + <7 28>, <8 29>, <11 30>, <12 31>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <4 58>, <7 54>, <11 55>, + <13 56>, <15 57>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpioe_l: gpio@1712 { + compatible = "nxp,siul2-gpio"; + reg = <0x1712 0x02>, <0x440 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 0>, <1 1>, <2 2>, <3 3>, + <4 4>, <5 5>, <6 6>, <8 7>, + <9 8>, <10 9>, <11 10>, <12 11>, + <13 12>, <14 13>, <15 14>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <0 30>, <2 31>, <5 36>, + <6 33>, <11 32>, <14 34>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpioe_h: gpio@1710 { + compatible = "nxp,siul2-gpio"; + reg = <0x1710 0x02>, <0x480 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 15>; + nxp,wkpu = <&wkpu>; + nxp,wkpu-interrupts = <0 23>, <2 59>, <5 60>, + <7 61>, <9 62>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpiof_l: gpio@1716 { + compatible = "nxp,siul2-gpio"; + reg = <0x1716 0x02>, <0x4c0 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 0>, <1 1>, <2 2>, <3 3>, + <4 4>, <5 5>, <6 6>, <7 7>, + <8 16>, <9 17>, <10 18>, <11 19>, + <12 20>, <13 21>, <14 22>, <15 23>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpiof_h: gpio@1714 { + compatible = "nxp,siul2-gpio"; + reg = <0x1714 0x02>, <0x500 0x40>; + reg-names = "pgpdo", "mscr"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpiog_l: gpio@171a { + compatible = "nxp,siul2-gpio"; + reg = <0x171a 0x02>, <0x540 0x40>; + reg-names = "pgpdo", "mscr"; + interrupt-parent = <&eirq0>; + interrupts = <0 8>, <1 9>, <2 10>, <3 11>, + <4 12>, <5 13>, <6 14>, <7 15>, + <8 24>, <9 25>, <10 26>, <11 27>, + <12 28>, <13 29>, <14 30>, <15 31>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + gpiog_h: gpio@1718 { + compatible = "nxp,siul2-gpio"; + reg = <0x1718 0x02>, <0x580 0x40>; + reg-names = "pgpdo", "mscr"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + }; + + stcu: stcu@3a0000 { + compatible = "nxp,stcu"; + reg = <0x3a0000 0x2260>; + status = "disabled"; + }; + + stm_0: stm@274000 { + compatible = "nxp,stm"; + reg = <0x274000 0x68>; + interrupts = <39 0>; + status = "disabled"; + }; + + stm_1: stm@474000 { + compatible = "nxp,stm"; + reg = <0x474000 0x68>; + interrupts = <40 0>; + status = "disabled"; + }; + + swt_0: swt@270000 { + compatible = "nxp,swt"; + reg = <0x270000 0x3c>; + interrupts = <42 0>; + status = "disabled"; + }; + + sxosc: sxosc@402cc000 { + compatible = "nxp,sxosc"; + reg = <0x402cc000 0x24>; + status = "disabled"; + }; + + tempsense: tempsense@37c000 { + compatible = "nxp,tempsense"; + reg = <0x37c000 0x30>; + status = "disabled"; + }; + + trgmux: trgmux@80000 { + compatible = "nxp,trgmux"; + reg = <0x80000 0xbc>; + status = "disabled"; + }; + + tspc: tspc@2c4000 { + compatible = "nxp,tspc"; + reg = <0x2c4000 0xc4>; + status = "disabled"; + }; + + virt_wrapper: virt-wrapper@2a8000 { + compatible = "nxp,virt-wrapper"; + reg = <0x2a8000 0x124>; + status = "disabled"; + }; + + wkpu: wkpu@2b4000 { + compatible = "nxp,wkpu"; + reg = <0x2b4000 0x90>; + interrupts = <83 0>; + status = "disabled"; + }; + + xbic_axbs: xbic@204000 { + compatible = "nxp,xbic"; + reg = <0x204000 0x2c>; + status = "disabled"; + }; + + xbic_axbs_edma: xbic@404000 { + compatible = "nxp,xbic"; + reg = <0x404000 0x2c>; + status = "disabled"; + }; + + xbic_axbs_peri: xbic@208000 { + compatible = "nxp,xbic"; + reg = <0x208000 0x2c>; + status = "disabled"; + }; + + xbic_axbs_tcm: xbic@400000 { + compatible = "nxp,xbic"; + reg = <0x400000 0x2c>; + status = "disabled"; + }; + + xrdc: xrdc@278000 { + compatible = "nxp,xrdc"; + reg = <0x278000 0x248c>; + status = "disabled"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/bindings/clock/nxp,firc.yaml b/dts/bindings/clock/nxp,firc.yaml new file mode 100644 index 0000000000000..ca57df3a55238 --- /dev/null +++ b/dts/bindings/clock/nxp,firc.yaml @@ -0,0 +1,18 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: Fast internal RC oscillator + +compatible: "nxp,firc" + +include: [base.yaml] + +properties: + reg: + required: true + + firc-div: + required: true + type: string + description: FIRC_DIV_SEL + enum: ["NULL", "DivBy2", "DivBy16", "UnDiv"] diff --git a/dts/bindings/clock/nxp,fxosc.yaml b/dts/bindings/clock/nxp,fxosc.yaml new file mode 100644 index 0000000000000..9362d431bf197 --- /dev/null +++ b/dts/bindings/clock/nxp,fxosc.yaml @@ -0,0 +1,33 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: Fast external crystal oscillator + +compatible: "nxp,fxosc" + +include: [base.yaml] + +properties: + reg: + required: true + + freq: + required: true + type: int + description: FXOSC output clock frequency in Hz + + workmode: + required: true + type: string + description: FXOSC work mode setting + enum: ["crystal", "bypass"] + + delay: + required: true + type: int + description: FXOSC startup delay in counts + + overdrive: + required: true + type: int + description: FXOSC overdrive protection setting diff --git a/dts/bindings/clock/nxp,mc-cgm.yaml b/dts/bindings/clock/nxp,mc-cgm.yaml new file mode 100644 index 0000000000000..0a53a94d82a59 --- /dev/null +++ b/dts/bindings/clock/nxp,mc-cgm.yaml @@ -0,0 +1,65 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: Glitchless clock switching Clock Generation module + +compatible: "nxp,mc-cgm" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + max-ido-change: + required: true + type: int + description: | + Maximum variation of current per time (mA/microsec) - max allowable + IDD change is determined by the user's power supply design. + + step-duration: + required: true + type: int + description: Step duration of each PCFS step (time per step in us). + + clk-src-freq: + required: true + type: int + description: | + Frequency of the clock source from which ramp-down and to which ramp-up are processed. + + mux-0-dc-0-div: + type: int + description: MUX_0_DC_0 divider setting + + mux-0-dc-1-div: + type: int + description: MUX_0_DC_1 divider setting + + mux-0-dc-2-div: + type: int + description: MUX_0_DC_2 divider setting + + mux-0-dc-3-div: + type: int + description: MUX_0_DC_3 divider setting + + mux-0-dc-4-div: + type: int + description: MUX_0_DC_4 divider setting + + mux-0-dc-5-div: + type: int + description: MUX_0_DC_5 divider setting + + mux-0-dc-6-div: + type: int + description: MUX_0_DC_6 divider setting + + "#clock-cells": + type: int + const: 1 + +clock-cells: + - name diff --git a/dts/bindings/clock/nxp,plldig.yaml b/dts/bindings/clock/nxp,plldig.yaml new file mode 100644 index 0000000000000..23d17e87050d8 --- /dev/null +++ b/dts/bindings/clock/nxp,plldig.yaml @@ -0,0 +1,61 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: Phase-locked loop + +compatible: "nxp,plldig" + +include: [base.yaml] + +properties: + reg: + required: true + + workmode: + required: true + type: string + description: PLL work mode setting + enum: ["Integer", "Fractional", "SSCG"] + + prediv: + required: true + type: int + description: Input Clock Predivider + + postdiv: + required: true + type: int + description: VCO clock post divider for driving the PHI output clock. + + multiplier: + required: true + type: int + description: Multiplication factor applied to the reference frequency + + fracloopdiv: + required: true + type: int + description: Numerator Of Fractional Loop Division Factor. + Value should less than 18432. + + stepsize: + required: true + type: int + description: For SSCG mode. Frequency Modulation Step Size + + stepnum: + required: true + type: int + description: | + For SSCG mode. Number Of Steps Of Modulation Period Or Frequency Modulation + + accuracy: + required: true + type: string + description: PLL unlock accuracy + enum: ["Accuracy9", "Accuracy17", "Accuracy33", "Accuracy5"] + + outdiv: + required: true + type: array + description: PLL Output Divider diff --git a/dts/bindings/pinctrl/nxp,mcxe31x-siul2-pinctrl.yaml b/dts/bindings/pinctrl/nxp,mcxe31x-siul2-pinctrl.yaml new file mode 100644 index 0000000000000..43b24d7b3c780 --- /dev/null +++ b/dts/bindings/pinctrl/nxp,mcxe31x-siul2-pinctrl.yaml @@ -0,0 +1,115 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + NXP SIUL2 Pin Controller for MCXE31X SoCs + + The NXP SIUL2 pin controller is a singleton node responsible for controlling + the pin function selection and pin properties. This node, labeled 'pinctrl' in + the SoC's devicetree, will define pin configurations in pin groups. Each group + within the pin configuration defines the pin configuration for a peripheral, + and each numbered subgroup in the pin group defines all the pins for that + peripheral with the same configuration properties. The 'pinmux' property in + a group selects the pins to be configured, and the remaining properties set + configuration values for those pins. + + For example, to configure the pinmux for UART0, modify the 'pinctrl' from your + board or application devicetree overlay as follows: + + /* Include the SoC package header containing the predefined pins definitions */ + #include + + &pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + }; + + The 'uart0_default' node contains the pin configurations for a particular state + of a device. The 'default' state is the active state. Other states for the same + device can be specified in separate child nodes of 'pinctrl'. + + In addition to 'pinmux' property, each group can contain other properties such as + 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in + 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the + output buffer use 'output-enable'. + + To link the pin configurations with UART0 device, use pinctrl-N property in the + device node, where 'N' is the zero-based state index (0 is the default state). + Following previous example: + + &uart0 { + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; + }; + + If only the required properties are supplied, the pin configuration register + will be assigned the following values: + - input and output buffers disabled + - internal pull not enabled + - slew rate "fastest" + - invert disabled + - drive strength disabled. + + Additionally, following settings are currently not supported and default to + the values indicated below: + - Safe Mode Control (disabled) + - Pad Keeping (disabled) + - Input Filter (disabled). + +compatible: "nxp,mcxe31x-siul2-pinctrl" + +include: base.yaml + +child-binding: + description: NXP SIUL2 pin controller pin group. + child-binding: + description: NXP SIUL2 pin controller pin configuration node. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-down + - bias-pull-up + - input-enable + - output-enable + + properties: + pinmux: + required: true + type: array + description: | + An array of pins sharing the same group properties. The pins must be + defined using the macros from the SoC package header. These macros + encode all the pin muxing information in a 32-bit value. + + slew-rate: + type: string + enum: + - "fastest" + - "slowest" + default: "fastest" + description: | + Slew rate control. Can be either slowest or fastest setting. + See the SoC reference manual for applicability of this setting. + + nxp,invert: + type: boolean + description: | + Invert the signal selected by Source Signal Selection (SSS) before + transmitting it to the associated destination (chip pin or module port). + + nxp,drive-strength: + type: boolean + description: | + Drive strength enable. + See the SoC reference manual for applicability of this setting. diff --git a/include/zephyr/drivers/clock_control/nxp_clock_control.h b/include/zephyr/drivers/clock_control/nxp_clock_control.h new file mode 100644 index 0000000000000..17d6544053ced --- /dev/null +++ b/include/zephyr/drivers/clock_control/nxp_clock_control.h @@ -0,0 +1,53 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_NXP_CLOCK_CONTROL_H_ +#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_NXP_CLOCK_CONTROL_H_ + +#include + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(mc_cgm), nxp_mc_cgm, okay) +#include +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(firc), nxp_firc, okay) +#define NXP_FIRC_DIV DT_ENUM_IDX(DT_NODELABEL(firc), firc_div) +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(fxosc), nxp_fxosc, okay) +#define NXP_FXOSC_FREQ DT_PROP(DT_NODELABEL(fxosc), freq) +#define NXP_FXOSC_WORKMODE \ + (DT_ENUM_IDX(DT_NODELABEL(fxosc), workmode) == 0 ? kFXOSC_ModeCrystal : kFXOSC_ModeBypass) +#define NXP_FXOSC_DELAY DT_PROP(DT_NODELABEL(fxosc), delay) +#define NXP_FXOSC_OVERDRIVE DT_PROP(DT_NODELABEL(fxosc), overdrive) +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), nxp_plldig, okay) +#define NXP_PLL_WORKMODE DT_ENUM_IDX(DT_NODELABEL(pll), workmode) +#define NXP_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv) +#define NXP_PLL_POSTDIV DT_PROP(DT_NODELABEL(pll), postdiv) +#define NXP_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), multiplier) +#define NXP_PLL_FRACLOOPDIV DT_PROP(DT_NODELABEL(pll), fracloopdiv) +#define NXP_PLL_STEPSIZE DT_PROP(DT_NODELABEL(pll), stepsize) +#define NXP_PLL_STEPNUM DT_PROP(DT_NODELABEL(pll), stepnum) +#define NXP_PLL_ACCURACY DT_ENUM_IDX(DT_NODELABEL(pll), accuracy) +#define NXP_PLL_OUTDIV_POINTER DT_PROP(DT_NODELABEL(pll), outdiv) +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(mc_cgm), nxp_mc_cgm, okay) +#define NXP_PLL_MAXIDOCHANGE DT_PROP(DT_NODELABEL(mc_cgm), max_ido_change) +#define NXP_PLL_STEPDURATION DT_PROP(DT_NODELABEL(mc_cgm), step_duration) +#define NXP_PLL_CLKSRCFREQ DT_PROP(DT_NODELABEL(mc_cgm), clk_src_freq) +#define NXP_PLL_MUX_0_DC_0_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_0_div) +#define NXP_PLL_MUX_0_DC_1_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_1_div) +#define NXP_PLL_MUX_0_DC_2_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_2_div) +#define NXP_PLL_MUX_0_DC_3_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_3_div) +#define NXP_PLL_MUX_0_DC_4_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_4_div) +#define NXP_PLL_MUX_0_DC_5_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_5_div) +#define NXP_PLL_MUX_0_DC_6_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_6_div) +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_NXP_CLOCK_CONTROL_H_ */ diff --git a/include/zephyr/dt-bindings/clock/nxp_mc_cgm.h b/include/zephyr/dt-bindings/clock/nxp_mc_cgm.h new file mode 100644 index 0000000000000..65ef408a41a36 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/nxp_mc_cgm.h @@ -0,0 +1,101 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_MC_CGM_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_MC_CGM_H_ + +/* Note- clock identifiers in this file must be unique, + * as the driver uses them in a switch case + */ + +#define MCUX_MCXE31X_CLK_ID(high, low) ((high << 8) | (low)) + +/* These IDs are used within SOC macros, and thus cannot be defined + * using the standard MCUX_MCXE31X_CLK_ID form + */ +/* --------------------- System layer clock --------------------- */ +#define MCUX_CORESYS_CLK MCUX_MCXE31X_CLK_ID(0x00, 0x00) +#define MCUX_AIPSPLAT_CLK MCUX_MCXE31X_CLK_ID(0x01, 0x00) +#define MCUX_AIPSSLOW_CLK MCUX_MCXE31X_CLK_ID(0x02, 0x00) +#define MCUX_HSE_CLK MCUX_MCXE31X_CLK_ID(0x03, 0x00) +#define MCUX_DCM_CLK MCUX_MCXE31X_CLK_ID(0x04, 0x00) +#define MCUX_LBIST_CLK MCUX_MCXE31X_CLK_ID(0x05, 0x00) +#define MCUX_QSPI_CLK MCUX_MCXE31X_CLK_ID(0x06, 0x00) + +/* --------------------- MC_CGM clock --------------------- */ +#define MCUX_FIRC_CLK MCUX_MCXE31X_CLK_ID(0x10, 0x00) +#define MCUX_SIRC_CLK MCUX_MCXE31X_CLK_ID(0x11, 0x00) +#define MCUX_FXOSC_CLK MCUX_MCXE31X_CLK_ID(0x12, 0x00) +#define MCUX_SXOSC_CLK MCUX_MCXE31X_CLK_ID(0x13, 0x00) +#define MCUX_PLLPHI0_CLK MCUX_MCXE31X_CLK_ID(0x14, 0x00) +#define MCUX_PLLPHI1_CLK MCUX_MCXE31X_CLK_ID(0x14, 0x01) + +/* --------------------- Peripheral clock --------------------- */ +#define MCUX_ADC0_CLK MCUX_MCXE31X_CLK_ID(0x20, 0x00) +#define MCUX_ADC1_CLK MCUX_MCXE31X_CLK_ID(0x20, 0x01) +#define MCUX_ADC2_CLK MCUX_MCXE31X_CLK_ID(0x20, 0x02) + +#define MCUX_BCTU_CLK MCUX_MCXE31X_CLK_ID(0x21, 0x00) + +#define MCUX_CMP0_CLK MCUX_MCXE31X_CLK_ID(0x22, 0x00) +#define MCUX_CMP1_CLK MCUX_MCXE31X_CLK_ID(0x22, 0x01) +#define MCUX_CMP2_CLK MCUX_MCXE31X_CLK_ID(0x22, 0x02) + +#define MCUX_EMIOS_CLK MCUX_MCXE31X_CLK_ID(0x23, 0x00) + +#define MCUX_FLEXCAN0_CLK MCUX_MCXE31X_CLK_ID(0x24, 0x00) +#define MCUX_FLEXCAN1_CLK MCUX_MCXE31X_CLK_ID(0x24, 0x01) +#define MCUX_FLEXCAN2_CLK MCUX_MCXE31X_CLK_ID(0x24, 0x02) +#define MCUX_FLEXCAN3_CLK MCUX_MCXE31X_CLK_ID(0x24, 0x03) +#define MCUX_FLEXCAN4_CLK MCUX_MCXE31X_CLK_ID(0x24, 0x04) +#define MCUX_FLEXCAN5_CLK MCUX_MCXE31X_CLK_ID(0x24, 0x05) + +#define MCUX_FLEXIO_CLK MCUX_MCXE31X_CLK_ID(0x25, 0x00) + +#define MCUX_LPI2C0_CLK MCUX_MCXE31X_CLK_ID(0x26, 0x00) +#define MCUX_LPI2C1_CLK MCUX_MCXE31X_CLK_ID(0x26, 0x01) + +#define MCUX_LPSPI0_CLK MCUX_MCXE31X_CLK_ID(0x27, 0x00) +#define MCUX_LPSPI1_CLK MCUX_MCXE31X_CLK_ID(0x27, 0x01) +#define MCUX_LPSPI2_CLK MCUX_MCXE31X_CLK_ID(0x27, 0x02) +#define MCUX_LPSPI3_CLK MCUX_MCXE31X_CLK_ID(0x27, 0x03) +#define MCUX_LPSPI4_CLK MCUX_MCXE31X_CLK_ID(0x27, 0x04) +#define MCUX_LPSPI5_CLK MCUX_MCXE31X_CLK_ID(0x27, 0x05) + +#define MCUX_LPUART0_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x00) +#define MCUX_LPUART1_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x01) +#define MCUX_LPUART2_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x02) +#define MCUX_LPUART3_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x03) +#define MCUX_LPUART4_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x04) +#define MCUX_LPUART5_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x05) +#define MCUX_LPUART6_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x06) +#define MCUX_LPUART7_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x07) +#define MCUX_LPUART8_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x08) +#define MCUX_LPUART9_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x09) +#define MCUX_LPUART10_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x0A) +#define MCUX_LPUART11_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x0B) +#define MCUX_LPUART12_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x0C) +#define MCUX_LPUART13_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x0D) +#define MCUX_LPUART14_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x0E) +#define MCUX_LPUART15_CLK MCUX_MCXE31X_CLK_ID(0x28, 0x0F) + +#define MCUX_PIT0_CLK MCUX_MCXE31X_CLK_ID(0x29, 0x00) +#define MCUX_PIT1_CLK MCUX_MCXE31X_CLK_ID(0x29, 0x01) +#define MCUX_PIT2_CLK MCUX_MCXE31X_CLK_ID(0x29, 0x02) + +#define MCUX_SAI0_CLK MCUX_MCXE31X_CLK_ID(0x2A, 0x00) +#define MCUX_SAI1_CLK MCUX_MCXE31X_CLK_ID(0x2A, 0x01) + +#define MCUX_STM0_CLK MCUX_MCXE31X_CLK_ID(0x2B, 0x00) +#define MCUX_STM1_CLK MCUX_MCXE31X_CLK_ID(0x2B, 0x01) + +/* --------------------- Partition 2 clock --------------------- */ +#define MCUX_QSPISF_CLK MCUX_MCXE31X_CLK_ID(0x2C, 0x00) +#define MCUX_EMACRX_CLK MCUX_MCXE31X_CLK_ID(0x2C, 0x01) +#define MCUX_EMACTX_CLK MCUX_MCXE31X_CLK_ID(0x2C, 0x02) +#define MCUX_EMACTS_CLK MCUX_MCXE31X_CLK_ID(0x2C, 0x03) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_MC_CGM_H_ */ diff --git a/modules/hal_nxp/mcux/Kconfig.mcux b/modules/hal_nxp/mcux/Kconfig.mcux index b9e8fd3b2da79..7d53f570a897e 100644 --- a/modules/hal_nxp/mcux/Kconfig.mcux +++ b/modules/hal_nxp/mcux/Kconfig.mcux @@ -8,7 +8,8 @@ config HAS_MCUX bool depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \ SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT || SOC_FAMILY_NXP_RW || \ - SOC_FAMILY_MCXN || SOC_FAMILY_MCXA || SOC_FAMILY_MCXW || SOC_FAMILY_MCXC + SOC_FAMILY_MCXN || SOC_FAMILY_MCXA || SOC_FAMILY_MCXW || SOC_FAMILY_MCXC || \ + SOC_FAMILY_MCXE if HAS_MCUX diff --git a/soc/nxp/mcx/mcxe/CMakeLists.txt b/soc/nxp/mcx/mcxe/CMakeLists.txt new file mode 100644 index 0000000000000..83badc015b8e1 --- /dev/null +++ b/soc/nxp/mcx/mcxe/CMakeLists.txt @@ -0,0 +1,7 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/nxp/mcx/mcxe/Kconfig b/soc/nxp/mcx/mcxe/Kconfig new file mode 100644 index 0000000000000..2a1d867fd5876 --- /dev/null +++ b/soc/nxp/mcx/mcxe/Kconfig @@ -0,0 +1,8 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MCXE + +rsource "*/Kconfig" + +endif #SOC_FAMILY_MCXE diff --git a/soc/nxp/mcx/mcxe/Kconfig.defconfig b/soc/nxp/mcx/mcxe/Kconfig.defconfig new file mode 100644 index 0000000000000..d7a6613d4a183 --- /dev/null +++ b/soc/nxp/mcx/mcxe/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MCXE + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_MCXE diff --git a/soc/nxp/mcx/mcxe/Kconfig.soc b/soc/nxp/mcx/mcxe/Kconfig.soc new file mode 100644 index 0000000000000..f1755af7e2c54 --- /dev/null +++ b/soc/nxp/mcx/mcxe/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MCXE + bool + +config SOC_FAMILY + default "mcxe" if SOC_FAMILY_MCXE + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/mcx/mcxe/mcxe31x/CMakeLists.txt b/soc/nxp/mcx/mcxe/mcxe31x/CMakeLists.txt new file mode 100644 index 0000000000000..87492e293b75d --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/CMakeLists.txt @@ -0,0 +1,18 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +zephyr_sources(soc.c) +zephyr_sources(sram_config.c) +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_SOC_RESET_HOOK mcxe31x_soc_initialization.S) + +zephyr_linker_sources_ifdef(CONFIG_NXP_MCXE31X_BOOT_HEADER + ROM_START SORT_KEY 0 boot_header.ld) + +zephyr_linker_sources(SECTIONS itcm.ld) +zephyr_code_relocate(FILES sram_config.c LOCATION ${CONFIG_SRAM_CONFIG_RELOCATE_MEM}_TEXT) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/mcx/mcxe/mcxe31x/Kconfig b/soc/nxp/mcx/mcxe/mcxe31x/Kconfig new file mode 100644 index 0000000000000..b23777d25b0c8 --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/Kconfig @@ -0,0 +1,50 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MCXE31X + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select ARM + select CLOCK_CONTROL + select HAS_MCUX + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select SOC_RESET_HOOK + select SOC_EARLY_INIT_HOOK + select CODE_DATA_RELOCATION + +if SOC_SERIES_MCXE31X + +if CODE_DATA_RELOCATION + +config SRAM_CONFIG_RELOCATE_MEM + string + default "ITCM" + help + Select memory to relocate sram_config.c code + +endif # CODE_DATA_RELOCATION + +if NXP_MCXE31X_BOOT_HEADER + +config BOOT_HEADER_OFFSET + hex "Flash config data offset" + default 0x0 + help + The flash config offset provides the boot ROM with the on-board + flash type and parameters. The boot ROM requires a fixed flash config + offset for FlexSPI device. + +config IMAGE_VECTOR_TABLE_OFFSET + hex "Image vector table offset" + default 0x1000 + help + The Image Vector Table (IVT) provides the boot ROM with pointers to + the application entry point and device configuration data. The boot + ROM requires a fixed IVT offset for each type of boot device. + +endif # NXP_MCXE31X_BOOT_HEADER + +endif # SOC_SERIES_MCXE31X diff --git a/soc/nxp/mcx/mcxe/mcxe31x/Kconfig.defconfig b/soc/nxp/mcx/mcxe/mcxe31x/Kconfig.defconfig new file mode 100644 index 0000000000000..2e00f0115b1a8 --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MCXE31X + +config NUM_IRQS + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK + +config CORTEX_M_SYSTICK + default n if (MCUX_LPTMR_TIMER || MCUX_OS_TIMER) + +config ROM_START_OFFSET + default 0x1000 + +endif # SOC_SERIES_MCXE31X diff --git a/soc/nxp/mcx/mcxe/mcxe31x/Kconfig.soc b/soc/nxp/mcx/mcxe/mcxe31x/Kconfig.soc new file mode 100644 index 0000000000000..8e6caff06622f --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/Kconfig.soc @@ -0,0 +1,68 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MCXE31X + bool + select SOC_FAMILY_MCXE + +config SOC_SERIES + default "mcxe31x" if SOC_SERIES_MCXE31X + +config SOC_MCXE315 + bool + select SOC_SERIES_MCXE31X + +config SOC_MCXE316 + bool + select SOC_SERIES_MCXE31X + +config SOC_MCXE317 + bool + select SOC_SERIES_MCXE31X + +config SOC_MCXE31B + bool + select SOC_SERIES_MCXE31X + +config SOC + default "mcxe315" if SOC_MCXE315 + default "mcxe316" if SOC_MCXE316 + default "mcxe317" if SOC_MCXE317 + default "mcxe31b" if SOC_MCXE31B + +config SOC_PART_NUMBER_MCXE315MLF + bool + select SOC_MCXE315 + +config SOC_PART_NUMBER_MCXE315MPA + bool + select SOC_MCXE315 + +config SOC_PART_NUMBER_MCXE316MLF + bool + select SOC_MCXE316 + +config SOC_PART_NUMBER_MCXE316MPA + bool + select SOC_MCXE316 + +config SOC_PART_NUMBER_MCXE317MPA + bool + select SOC_MCXE317 + +config SOC_PART_NUMBER_MCXE317MPB + bool + select SOC_MCXE317 + +config SOC_PART_NUMBER_MCXE31BMPB + bool + select SOC_MCXE31B + +config SOC_PART_NUMBER + default "MCXE315MLF" if SOC_PART_NUMBER_MCXE315MLF + default "MCXE315MPA" if SOC_PART_NUMBER_MCXE315MPA + default "MCXE316MLF" if SOC_PART_NUMBER_MCXE316MLF + default "MCXE316MPA" if SOC_PART_NUMBER_MCXE316MPA + default "MCXE317MPA" if SOC_PART_NUMBER_MCXE317MPA + default "MCXE317MPB" if SOC_PART_NUMBER_MCXE317MPB + default "MCXE31BMPB" if SOC_PART_NUMBER_MCXE31BMPB diff --git a/soc/nxp/mcx/mcxe/mcxe31x/boot_header.ld b/soc/nxp/mcx/mcxe/mcxe31x/boot_header.ld new file mode 100644 index 0000000000000..129d7db81af3c --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/boot_header.ld @@ -0,0 +1,8 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +. += CONFIG_BOOT_HEADER_OFFSET - (. - __rom_start_address); +KEEP(*(.boot_header)) diff --git a/soc/nxp/mcx/mcxe/mcxe31x/itcm.ld b/soc/nxp/mcx/mcxe/mcxe31x/itcm.ld new file mode 100644 index 0000000000000..a3bc678710315 --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/itcm.ld @@ -0,0 +1,13 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_PROLOGUE(.itcm_text,,) +{ + . = ALIGN(4); + _itcm_text_start = .; + KEEP(*(.itcm_text)) + _itcm_text_end = .; +} GROUP_LINK_IN(ITCM) diff --git a/soc/nxp/mcx/mcxe/mcxe31x/mcxe31x_soc_initialization.S b/soc/nxp/mcx/mcxe/mcxe31x/mcxe31x_soc_initialization.S new file mode 100644 index 0000000000000..44f3617569de8 --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/mcxe31x_soc_initialization.S @@ -0,0 +1,115 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#define MC_RGM_BASE DT_REG_ADDR(DT_NODELABEL(mc_rgm)) +#define MC_RGM_DES 0x0 +#define MC_RGM_FES 0x8 + +_ASM_FILE_PROLOGUE + +GTEXT(soc_reset_hook) + +SECTION_FUNC(TEXT, soc_reset_hook) + + /* + * On destructive reset, SRAM and TCM memories must be initialized to a known value using a + * 64-bit master before 32-bit masters can read or write to them. Note that SRAM retains + * content during functional reset through a hardware mechanism, therefore accesses do not + * cause any content corruption errors. + * + * This is implemented directly in ASM, to ensure no stack access is performed. + */ + + /* If we come from a destructive reset, then ignore functional reset flags */ + ldr r1, =MC_RGM_BASE + ldr r2, [r1, MC_RGM_DES] + cmp r2, 0x0 + bne ECC_INIT + ldr r2, [r1, MC_RGM_FES] + cmp r2, 0x0 + bne ECC_END + +ECC_INIT: + ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) + ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) + + subs r2, #1 + + ble SRAM_LOOP_END + + movs r0, 0 + movs r3, 0 + +SRAM_LOOP: + stm r1!, {r0,r3} + subs r2, 8 + bge SRAM_LOOP + +SRAM_LOOP_END: + +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay) + + ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_itcm)) + ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_itcm)) + + subs r2, #1 + +ITCM_LOOP: + stm r1!, {r0,r3} + subs r2, 8 + bge ITCM_LOOP +#endif + +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay) + + ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm)) + ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm)) + + subs r2, #1 + +DTCM_LOOP: + stm r1!, {r0,r3} + subs r2, 8 + bge DTCM_LOOP +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(itcm1), okay) + + ldr r1, = DT_REG_ADDR(DT_NODELABEL(itcm1)) + ldr r2, = DT_REG_SIZE(DT_NODELABEL(itcm1)) + + subs r2, #1 + +ITCM1_LOOP: + stm r1!, {r0,r3} + subs r2, 8 + bge ITCM1_LOOP +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(dtcm1), okay) + + ldr r1, = DT_REG_ADDR(DT_NODELABEL(dtcm1)) + ldr r2, = DT_REG_SIZE(DT_NODELABEL(dtcm1)) + + subs r2, #1 + +DTCM1_LOOP: + stm r1!, {r0,r3} + subs r2, 8 + bge DTCM1_LOOP +#endif + +ECC_END: + /* save lr value to r4 */ + mov r4, lr + /* Jump to SystemInit function*/ + bl SystemInit + mov lr, r4 + bx lr diff --git a/soc/nxp/mcx/mcxe/mcxe31x/pinctrl_soc.h b/soc/nxp/mcx/mcxe/mcxe31x/pinctrl_soc.h new file mode 100644 index 0000000000000..9f1b56c5d9d68 --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/pinctrl_soc.h @@ -0,0 +1,32 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_NXP_MCXE31X_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_NXP_MCXE31X_PINCTRL_SOC_H_ + +#include +#include +#include + +#define NXP_SIUL2_PINMUX_INIT(group, value) \ + .mscr = {.inst = NXP_SIUL2_PINMUX_GET_MSCR_SIUL2_IDX(value), \ + .idx = NXP_SIUL2_PINMUX_GET_MSCR_IDX(value), \ + .val = SIUL2_MSCR_SSS(NXP_SIUL2_PINMUX_GET_MSCR_SSS(value)) | \ + SIUL2_MSCR_OBE(DT_PROP(group, output_enable)) | \ + SIUL2_MSCR_IBE(DT_PROP(group, input_enable)) | \ + SIUL2_MSCR_PUE(DT_PROP(group, bias_pull_up) || \ + DT_PROP(group, bias_pull_down)) | \ + SIUL2_MSCR_PUS(DT_PROP(group, bias_pull_up)) | \ + SIUL2_MSCR_SRC(DT_ENUM_IDX(group, slew_rate)) | \ + SIUL2_MSCR_DSE(DT_PROP(group, nxp_drive_strength)) | \ + SIUL2_MSCR_INV(DT_PROP(group, nxp_invert))}, \ + .imcr = { \ + .inst = NXP_SIUL2_PINMUX_GET_IMCR_SIUL2_IDX(value), \ + .idx = NXP_SIUL2_PINMUX_GET_IMCR_IDX(value), \ + .val = SIUL2_IMCR_SSS(NXP_SIUL2_PINMUX_GET_IMCR_SSS(value)), \ + } + +#endif /* ZEPHYR_SOC_NXP_MCXE31X_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/mcx/mcxe/mcxe31x/soc.c b/soc/nxp/mcx/mcxe/mcxe31x/soc.c new file mode 100644 index 0000000000000..c7a2ebeddbd22 --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/soc.c @@ -0,0 +1,40 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for nxp_mcxe platform + * + * This module provides routines to initialize and support board-level + * hardware for the nxp_mcxe platform. + */ + +#include +#include +#include +#include +#include "soc.h" + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the counter device driver, if required. + * + * @return 0 + */ +void soc_early_init_hook(void) +{ +#ifdef CONFIG_SOC_MCXE31B + enable_sram_extra_latency(true); +#else + enable_sram_extra_latency(false); +#endif + /* Enable I/DCache */ + sys_cache_instr_enable(); + sys_cache_data_enable(); +} diff --git a/soc/nxp/mcx/mcxe/mcxe31x/soc.h b/soc/nxp/mcx/mcxe/mcxe31x/soc.h new file mode 100644 index 0000000000000..341a3b6cb6942 --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/soc.h @@ -0,0 +1,26 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#ifndef _ASMLANGUAGE + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void enable_sram_extra_latency(bool en); + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/mcx/mcxe/mcxe31x/sram_config.c b/soc/nxp/mcx/mcxe/mcxe31x/sram_config.c new file mode 100644 index 0000000000000..c3f01a48911a3 --- /dev/null +++ b/soc/nxp/mcx/mcxe/mcxe31x/sram_config.c @@ -0,0 +1,24 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "fsl_common.h" + +/* Don't access system RAM when configuring PRAM FT_DIS. */ +void enable_sram_extra_latency(bool en) +{ + if (en) { + /* Configure SRAM read wait states. */ + PRAMC_0->PRCR1 |= PRAMC_PRCR1_FT_DIS_MASK; +#if defined(PRAMC_1) + PRAMC_1->PRCR1 |= PRAMC_PRCR1_FT_DIS_MASK; +#endif + } else { + PRAMC_0->PRCR1 &= ~PRAMC_PRCR1_FT_DIS_MASK; +#if defined(PRAMC_1) + PRAMC_1->PRCR1 &= ~PRAMC_PRCR1_FT_DIS_MASK; +#endif + } +} diff --git a/soc/nxp/mcx/soc.yml b/soc/nxp/mcx/soc.yml index 23bce577c193a..c4cb4ddac4979 100644 --- a/soc/nxp/mcx/soc.yml +++ b/soc/nxp/mcx/soc.yml @@ -16,6 +16,14 @@ family: - name: mcxc142 - name: mcxc242 - name: mcxc444 +- name: mcxe + series: + - name: mcxe31x + socs: + - name: mcxe315 + - name: mcxe316 + - name: mcxe317 + - name: mcxe31b - name: mcxa socs: - name: mcxa153 diff --git a/tests/drivers/gpio/gpio_basic_api/boards/frdm_mcxe31b.overlay b/tests/drivers/gpio/gpio_basic_api/boards/frdm_mcxe31b.overlay new file mode 100644 index 0000000000000..f84a3a74f4304 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/frdm_mcxe31b.overlay @@ -0,0 +1,29 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + status = "okay"; + out-gpios = <&arduino_header 0 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL | GPIO_PULL_UP)>; + in-gpios = <&arduino_header 1 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL | GPIO_PULL_UP)>; + }; +}; + +&gpioe_l { + status = "okay"; +}; + +&gpioe_h { + status = "okay"; +}; + +&eirq0_default { + group2 { + pinmux = ; + input-enable; + }; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/testcase.yaml b/tests/drivers/gpio/gpio_basic_api/testcase.yaml index 013fd09f45bda..ec44caf07d663 100644 --- a/tests/drivers/gpio/gpio_basic_api/testcase.yaml +++ b/tests/drivers/gpio/gpio_basic_api/testcase.yaml @@ -58,6 +58,7 @@ tests: - frdm_k64f platform_exclude: # below boards are customized + - frdm_mcxe31b - mimxrt595_evk/mimxrt595s/cm33 - mimxrt1020_evk - mimxrt1040_evk @@ -75,6 +76,7 @@ tests: - arduino_gpio filter: dt_compat_enabled("test-gpio-basic-api") and dt_compat_enabled("arduino-header-r3") platform_allow: + - frdm_mcxe31b - mimxrt595_evk/mimxrt595s/cm33 - mimxrt1020_evk - mimxrt1040_evk diff --git a/west.yml b/west.yml index 8ddf3001a042d..086659ca0e4c1 100644 --- a/west.yml +++ b/west.yml @@ -210,7 +210,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 4377ecfba52fe0ff7352eadf426b523ed3e1d27f + revision: f33ec8f8b2c7ff9f322fabd23ba8639daa2610eb path: modules/hal/nxp groups: - hal