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Enable LMEM cache for MCXE247.


int cache_instr_invd_range(void *addr, size_t size)
{
L1CACHE_InvalidateCodeCacheByRange((uint32_t)addr, size);
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nit: you might want to also caste size to uint32_t since the underlying API defines it this way. Although I'm aware it is unlikely we would be building this for a 64bit platform.

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Add uint32_t for size.

dleach02
dleach02 previously approved these changes Oct 31, 2025
#include <zephyr/logging/log.h>
#include <fsl_cache.h>

LOG_MODULE_REGISTER(cache_nxp_lmem_cache, CONFIG_CACHE_LOG_LEVEL);
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can removed since log is not used?

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Removed

ZhaoxiangJin
ZhaoxiangJin previously approved these changes Nov 14, 2025
default y

# Enable cache management features
config CACHE_MANAGEMENT
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There is an initiative to use "configdefault" in this case: 5805685

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Updated to configdefault.

@dleach02
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@Holt-Sun lets address the compliance issues, merge conflicts, and twister errors.

…E24X

Select cache_lmem component for MCXE24X devices.
This exposes the LMEM cache API needed by the Zephyr driver

Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add LMEM cache driver implementing instruction cache ops.
Wire driver into cache Kconfig menu and CMake build.
Enables I-cache control on SoCs with NXP LMEM controller.

Signed-off-by: Holt Sun <holt.sun@nxp.com>
Select CPU_HAS_ICACHE and HAS_MCUX_LMEM_CACHE.
Default CACHE_MANAGEMENT=y and select EXTERNAL_CACHE.
Prepares MCXE24x to use the LMEM cache driver.

Signed-off-by: Holt Sun <holt.sun@nxp.com>
@Holt-Sun Holt-Sun force-pushed the mcxe247-enable-lmem-cache branch from c84c218 to a8b7c54 Compare November 19, 2025 02:30
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@Holt-Sun
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Hi @nashif , do you see anything that block the merge of this PR? Thank you.

@ZhaoxiangJin
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Hi @nashif , do you see anything that block the merge of this PR? Thank you.

PR needs get approval from assignee before merge.

@Holt-Sun
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Hi @nashif , do you see anything that block the merge of this PR? Thank you.

PR needs get approval from assignee before merge.

Thank you for the information.

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8 participants