diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index c0310850f0b8b..5524053bcd979 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3346,11 +3346,15 @@ Microchip RISC-V Platforms: - fkokosinski - kgugala - tgorochowik + - con-pax + - pmoussay-emdalo files: - boards/microchip/m2gl025_miv/ - boards/microchip/mpfs_icicle/ + - boards/microchip/pic64gx_curiosity_kit/ - dts/riscv/microchip/ - soc/microchip/miv/ + - soc/microchip/pic64/ labels: - "platform: Microchip RISC-V" diff --git a/boards/microchip/pic64gx_curiosity_kit/Kconfig.defconfig b/boards/microchip/pic64gx_curiosity_kit/Kconfig.defconfig new file mode 100644 index 0000000000000..e1d33d0c0015a --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/Kconfig.defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PIC64GX_CURIOSITY_KIT + +endif diff --git a/boards/microchip/pic64gx_curiosity_kit/Kconfig.pic64gx_curiosity_kit b/boards/microchip/pic64gx_curiosity_kit/Kconfig.pic64gx_curiosity_kit new file mode 100644 index 0000000000000..43944b72d6100 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/Kconfig.pic64gx_curiosity_kit @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PIC64GX_CURIOSITY_KIT + select SOC_PIC64GX1000_U54 if BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_U54 || \ + BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_U54_SMP + select SOC_PIC64GX1000_E51 if BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_E51 diff --git a/boards/microchip/pic64gx_curiosity_kit/board.cmake b/boards/microchip/pic64gx_curiosity_kit/board.cmake new file mode 100644 index 0000000000000..f7270b10e7f21 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/board.cmake @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(OPENOCD_USE_LOAD_IMAGE NO) + +board_runner_args(openocd --use-elf --no-load) + +if(CONFIG_BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_E51) + board_runner_args(openocd --gdb-client-port=3333) +elseif(CONFIG_BOARD_PIC64GX_CURIOSITY_KIT_PIC64GX1000_U54) + board_runner_args(openocd --gdb-client-port=3334) +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/microchip/pic64gx_curiosity_kit/board.yml b/boards/microchip/pic64gx_curiosity_kit/board.yml new file mode 100644 index 0000000000000..fd97106207256 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/board.yml @@ -0,0 +1,9 @@ +board: + name: pic64gx_curiosity_kit + full_name: pic64gx_curiosity_kit + vendor: microchip + socs: + - name: pic64gx1000 + variants: + - name: smp + cpucluster: u54 diff --git a/boards/microchip/pic64gx_curiosity_kit/doc/img/pic64gx_curiosity_kit.jpeg b/boards/microchip/pic64gx_curiosity_kit/doc/img/pic64gx_curiosity_kit.jpeg new file mode 100755 index 0000000000000..e5c9318a1d22b Binary files /dev/null and b/boards/microchip/pic64gx_curiosity_kit/doc/img/pic64gx_curiosity_kit.jpeg differ diff --git a/boards/microchip/pic64gx_curiosity_kit/doc/index.rst b/boards/microchip/pic64gx_curiosity_kit/doc/index.rst new file mode 100644 index 0000000000000..bffd30a45a18a --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/doc/index.rst @@ -0,0 +1,114 @@ +.. zephyr:board:: pic64gx_curiosity_kit + +Overview +******** + +The Microchip pic64gx_curiosity_kit board is a RISC-V based development board with a Microchip PIC64GX1000 SoC. +More information can be found on the `Microchip website `_. + +Programming and debugging +************************* + +Building +======== + +Applications for the ``pic64gx_curiosity_kit`` board configuration can be built as usual +(see :ref:`build_an_application`): + +.. zephyr-app-commands:: + :board: pic64gx_curiosity_kit/pic64gx1000/u54 + :goals: build + +.. zephyr-app-commands:: + :board: pic64gx_curiosity_kit/pic64gx1000/u54/smp + :goals: build + +Flashing +======== + +To Flash to the device, the easiest way to proceed is to load the binary using a sdcard. +The binary on the sdcard can then be loaded by the bootloader at the designated address. + +For the bootloader to be able to load the application, a payload file needs to be generated. +Please proceed as follows: + +To get the hss-payload-generator tool, please clone the following repository and build the tool: + +.. code-block:: bash + + git clone https://github.com/pic64gx/pic64gx-hart-software-services.git + cd pic64gx-hart-software-services/tools/hss-payload-generator + make + +To generate a payload: + +.. code-block:: bash + + ./hss-payload-generator -c config.yaml -v output.bin + +A payload generator config file such as the following should be used to generate a compatible with the Hart Software Services (HSS). +https://github.com/pic64gx/pic64gx-hart-software-services + +For single core: + +.. code-block:: yaml + + set-name: 'Zephyr-DDR' + + hart-entry-points: { + u54_1: '0x80000000' + } + + payloads: + build/zephyr/zephyr.elf: { + exec-addr: '0x80000000', + owner-hart: u54_1, + priv-mode: prv_m, + skip-opensbi: true, + payload-name: "zephyr" + } + +For SMP: + +.. code-block:: yaml + + set-name: 'Zephyr-SMP-DDR' + + hart-entry-points: { + u54_1: '0x80000000', + u54_2: '0x80000000', + u54_3: '0x80000000', + u54_4: '0x80000000' + } + + payloads: + build/zephyr/zephyr.elf: { + exec-addr: '0x80000000', + owner-hart: u54_1, + secondary-hart: u54_2, + secondary-hart: u54_3, + secondary-hart: u54_4, + priv-mode: prv_m, + skip-opensbi: true, + payload-name: "zephyr" + } + +Please refer to the following README.md for more information on playload generation: +https://github.com/pic64gx/pic64gx-hart-software-services/blob/pic64gx/tools/hss-payload-generator/README.md + +Then the output payload file needs to be copied to the sdcard (assuming the sdcard is mounted at /dev/sdx). + +.. code-block:: bash + + sudo dd if= of=/dev/sdx + +Debugging +========= + +Please note that in most use cases, the application must be loaded in the external DDR memory. +And therefore DDR must be initialized before loading the application or debugging the application. + +The way to proceed is to load the HSS firmware first, then load the application in DDR memory through +the HSS loader following the instructions in `Flashing`_. + +Then proceed to debug the application as usual (ie: :ref:`application_debugging`.) diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_common.dtsi b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_common.dtsi new file mode 100644 index 0000000000000..adfcadccf3f71 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_common.dtsi @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "Microchip PIC64GX Curiosity Kit"; + compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + aliases { + led0 = &led1; + sw0 = &sw1; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + soc { + dram: memory@80000000 { + compatible = "mmio-sram"; + reg = <0x80000000 0x40000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&gpio1 2 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_1"; + }; + led2: led2 { + gpios = <&gpio1 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_2"; + }; + led3: led3 { + gpios = <&gpio1 4 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_3"; + }; + led4: led4 { + gpios = <&gpio1 5 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_4"; + }; + led5: led5 { + gpios = <&gpio1 6 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_5"; + }; + led6: led6 { + gpios = <&gpio1 7 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_6"; + }; + led7: led7 { + gpios = <&gpio1 8 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_7"; + }; + led8: led8 { + gpios = <&gpio1 9 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + label = "LED_8"; + }; + }; + + keys { + compatible = "gpio-keys"; + sw1: sw1 { + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + label = "SW_1"; + zephyr,code = ; + }; + sw2: sw2 { + gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + label = "SW_2"; + zephyr,code = ; + }; + }; +}; + +&gpio1 { + status = "okay"; + mux-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>, <3 GPIO_ACTIVE_HIGH>, + <4 GPIO_ACTIVE_HIGH>, <5 GPIO_ACTIVE_HIGH>, + <6 GPIO_ACTIVE_HIGH>, <7 GPIO_ACTIVE_HIGH>, + <8 GPIO_ACTIVE_HIGH>, <9 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; + +&spi1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_defconfig b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_defconfig new file mode 100644 index 0000000000000..7fbceea82ba3a --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_FPU=n +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.dts b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.dts new file mode 100644 index 0000000000000..22eef350de5d3 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "pic64gx_curiosity_kit_common.dtsi" + +/ { + compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + + cpus { + cpu@1 { + status = "disabled"; + }; + + cpu@2 { + status = "disabled"; + }; + + cpu@3 { + status = "disabled"; + }; + + cpu@4 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &mmuart0; + zephyr,shell-uart = &mmuart0; + zephyr,sram = &dram; + }; +}; + +&mmuart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.yaml b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.yaml new file mode 100644 index 0000000000000..0a41b341b5084 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51.yaml @@ -0,0 +1,12 @@ +identifier: pic64gx_curiosity_kit/pic64gx1000/e51 +name: Microchip PIC64GX Curiosity kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: microchip diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51_defconfig b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51_defconfig new file mode 100644 index 0000000000000..baa93debb87fe --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_e51_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.dts b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.dts new file mode 100644 index 0000000000000..bca7e8338be6e --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "pic64gx_curiosity_kit_common.dtsi" + +/ { + compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; + + chosen { + zephyr,console = &mmuart1; + zephyr,shell-uart = &mmuart1; + zephyr,sram = &dram; + }; +}; + +&mmuart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.yaml b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.yaml new file mode 100644 index 0000000000000..9841884511aed --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54.yaml @@ -0,0 +1,12 @@ +identifier: pic64gx_curiosity_kit/pic64gx1000/u54 +name: Microchip PIC64GX Curiosity kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: microchip diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_defconfig b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_defconfig new file mode 100644 index 0000000000000..baa93debb87fe --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.dts b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.dts new file mode 100644 index 0000000000000..4a1b709c2253d --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.dts @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "pic64gx_curiosity_kit_pic64gx1000_u54.dts" + +/ { + compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + + chosen { + zephyr,console = &mmuart1; + zephyr,shell-uart = &mmuart1; + zephyr,sram = &dram; + }; +}; + +&mmuart1 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; +}; diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.yaml b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.yaml new file mode 100644 index 0000000000000..48d2e3e30e829 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp.yaml @@ -0,0 +1,12 @@ +identifier: pic64gx_curiosity_kit/pic64gx1000/u54/smp +name: Microchip PIC64GX Curiosity kit +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: microchip diff --git a/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp_defconfig b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp_defconfig new file mode 100644 index 0000000000000..e334980822cd1 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/pic64gx_curiosity_kit_pic64gx1000_u54_smp_defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +# GPIO driver options +CONFIG_GPIO=y +CONFIG_I2C=y +CONFIG_SMP=y diff --git a/boards/microchip/pic64gx_curiosity_kit/support/embedded_flashpro5.cfg b/boards/microchip/pic64gx_curiosity_kit/support/embedded_flashpro5.cfg new file mode 100644 index 0000000000000..416cbdb881846 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/support/embedded_flashpro5.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Embedded FlashPro5 custom configuration for PIC64GX Curiosity Kit +# + +adapter speed 6000 + +adapter driver ftdi + +ftdi vid_pid 0x1514 0x200a + +# That FTDI has 4 channels (channel 0 and 1 are MPSSE-capable, 2 and 3 are bitbang +ftdi channel 0 + +# Initial Layout - data[0..15] direction[0..15] +ftdi layout_init 0x0018 0xfdfb +# Signal Data Direction Notes +# AD0 TCK 0 1 (out) Port A TCK +# AD1 TDI 0 1 (out) Port A TDI +# AD2 TDO 0 0 (in) PORT A TDO +# AD3 TMS 1 1 (out) Port A TMS +# AD4 GPIOL0 1 1 (out) Port A TRST +# AD5 GPIOL1 0 1 (out) (unused) +# AD6 GPIOL2 0 1 (out) (unused) +# AD7 GPIOL3 0 1 (out) (unused) + +# BD0 TCK 0 1 (out) FTDI_UART_B_TXD +# BD1 TDI 0 0 (in) FTDI_UART_B_RXD +# BD2 TDO 0 1 (out) (unused) +# BD3 TMS 0 1 (out) (unused) +# BD4 GPIOL0 0 1 (out) (unused) +# BD5 GPIOL1 0 1 (out) (unused) +# BD6 GPIOL2 0 1 (out) (unused) +# BD7 GPIOL2 0 1 (out) (unused) + +# Signals definition +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 diff --git a/boards/microchip/pic64gx_curiosity_kit/support/openocd.cfg b/boards/microchip/pic64gx_curiosity_kit/support/openocd.cfg new file mode 100644 index 0000000000000..05b3d8bbcb4b5 --- /dev/null +++ b/boards/microchip/pic64gx_curiosity_kit/support/openocd.cfg @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: Apache-2.0 + +source [find embedded_flashpro5.cfg] + +# SPDX-License-Identifier: GPL-2.0-or-later + +#------------------------------------------------------------------------------ +# Microchip RISC-V +#------------------------------------------------------------------------------ + +set DEVICE pic64gx + +# PIC64GX hart id to name lookup table +array set pic64gx_hart_names { + 0 hart0_e51 + 1 hart1_u54_1 + 2 hart2_u54_2 + 3 hart3_u54_3 + 4 hart4_u54_4 +} + +# Device tapname tapname to IDCODE lookup tables + +# PIC64GX table +set pic64gx_tap_info { + PIC64GX1000 0x0f8531cf +} + +proc expected_ids {tap_list} { + set str "" + dict for {key value} $tap_list { + append str "-expected-id" " " $value " " + } + + return $str +} + +proc get_tap_type {idcode_in tap_list} { + set str "unknown" + set idcode "0x" + append idcode $idcode_in + + dict for {key value} $tap_list { + if {$value == $idcode} { + set str "" + append str $key " " "TAP" + } + } + + return $str +} + +# Process COREID variable +if {![exists COREID]} { + set COREID -1 +} + +# COREID +# For Multi-Hart setups, check COREID, default to -1 (single debug connection +# to all harts) if unspecified or invalid (out of range ) +proc handle_coreid {lower_bound upper_bound coreid} { + if {$coreid < $lower_bound || $coreid > $upper_bound} { + echo [format "Warn : COREID %s not in range ($lower_bound..$upper_bound), defaulting to -1 (single connection to all harts)" $coreid] + set coreid -1 + } + + return $coreid +} + +proc setup_pic64gx {device coreid tap_info hart_names } { + set coreid [handle_coreid -1 4 $coreid ] + + # RISC-V CPU DTM TAP + set irlen 8 + set expected_ids [expected_ids $tap_info] + eval jtag newtap $device cpu -irlen $irlen $expected_ids -ignore-version + + # PIC64GX + if {$coreid == -1} { + # Single debug connection to all harts + set _TARGETNAME_0 $device.$hart_names(0) + set _TARGETNAME_1 $device.$hart_names(1) + set _TARGETNAME_2 $device.$hart_names(2) + set _TARGETNAME_3 $device.$hart_names(3) + set _TARGETNAME_4 $device.$hart_names(4) + + target create $_TARGETNAME_0 riscv -chain-position $device.cpu -coreid 0 -rtos hwthread + target create $_TARGETNAME_1 riscv -chain-position $device.cpu -coreid 1 -rtos hwthread + target create $_TARGETNAME_2 riscv -chain-position $device.cpu -coreid 2 -rtos hwthread + target create $_TARGETNAME_3 riscv -chain-position $device.cpu -coreid 3 -rtos hwthread + target create $_TARGETNAME_4 riscv -chain-position $device.cpu -coreid 4 -rtos hwthread + target smp $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4 + + $_TARGETNAME_1 configure -event reset-init init_regs + $_TARGETNAME_2 configure -event reset-init init_regs + $_TARGETNAME_3 configure -event reset-init init_regs + $_TARGETNAME_4 configure -event reset-init init_regs + + } else { + # Debug connection to a specific hart + set _TARGETNAME_0 $device.$hart_names($coreid) + target create $_TARGETNAME_0 riscv -chain-position $device.cpu -coreid $coreid + } + + $_TARGETNAME_0 configure -event reset-init board_reset_init + $_TARGETNAME_0 configure -event reset-init init_regs + + # gdb-detach event handler + $_TARGETNAME_0 configure -event gdb-detach { + # resume execution on debugger detach + resume + } + + # + # Utility procedures + # + + proc board_reset_init {} { + # call board level reset-init if defined + if {[exists -proc do_board_reset_init]} { + do_board_reset_init + } + } + + proc init_regs {} { + reg pc 0 + } + + # + # Reset configuration + # + + # Only TRSTn supported + reset_config trst_only +} + +# Board specific initialization +proc do_board_reset_init {} { + # doesn't appear to be called +} + +echo [format "Info : Connecting to member of PIC64GX family"] +set ret [setup_pic64gx $DEVICE $COREID $pic64gx_tap_info $pic64gx_hart_names] diff --git a/dts/riscv/microchip/pic64gx.dtsi b/dts/riscv/microchip/pic64gx.dtsi new file mode 100644 index 0000000000000..03fc830c8cb82 --- /dev/null +++ b/dts/riscv/microchip/pic64gx.dtsi @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + clock-frequency = <0>; + compatible = "sifive,e51", "riscv"; + device_type = "cpu"; + reg = < 0x0 >; + riscv,isa = "rv64imac_zicsr_zifencei"; + hlic0: interrupt-controller { + compatible = "riscv,cpu-intc"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@1 { + clock-frequency = <0>; + compatible = "sifive,u54", "riscv"; + device_type = "cpu"; + reg = < 0x1 >; + riscv,isa = "rv64gc"; + hlic1: interrupt-controller { + compatible = "riscv,cpu-intc"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54", "riscv"; + device_type = "cpu"; + reg = < 0x2 >; + riscv,isa = "rv64gc"; + hlic2: interrupt-controller { + compatible = "riscv,cpu-intc"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54", "riscv"; + device_type = "cpu"; + reg = < 0x3 >; + riscv,isa = "rv64gc"; + hlic3: interrupt-controller { + compatible = "riscv,cpu-intc"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54", "riscv"; + device_type = "cpu"; + reg = < 0x4 >; + riscv,isa = "rv64gc"; + hlic4: interrupt-controller { + compatible = "riscv,cpu-intc"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + clint: clint@2000000 { + compatible = "sifive,clint0"; + interrupts-extended = <&hlic0 3 + &hlic1 3 + &hlic2 3 + &hlic3 3 + &hlic4 3>; + interrupt-names = "soft0", "soft1", "soft2", "soft3", + "soft4"; + reg = <0x2000000 0x10000>; + }; + + mtimer: timer@200bff8 { + compatible = "riscv,machine-timer"; + interrupts-extended = <&hlic0 7 + &hlic1 7 + &hlic2 7 + &hlic3 7 + &hlic4 7>; + reg = <0x200bff8 0x8 0x2004000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + + plic: interrupt-controller@c000000 { + compatible = "sifive,plic-1.0.0"; + #interrupt-cells = <2>; + #address-cells = <1>; + interrupt-controller; + interrupts-extended = <&hlic0 11 + &hlic1 11 &hlic1 9 + &hlic2 11 &hlic2 9 + &hlic3 11 &hlic3 9 + &hlic4 11 &hlic4 9>; + reg = <0x0c000000 0x04000000>; + riscv,max-priority = <7>; + riscv,ndev = <185>; + }; + + mmuart0: serial@20000000 { + compatible = "ns16550"; + reg = <0x20000000 0x1000>; + clock-frequency = <150000000>; + current-speed = <115200>; + interrupt-parent = <&plic>; + interrupts = <90 1>; + reg-shift = <2>; + status = "disabled"; + }; + + mmuart1: serial@20100000 { + compatible = "ns16550"; + reg = <0x20100000 0x1000>; + clock-frequency = <150000000>; + current-speed = <115200>; + interrupt-parent = <&plic>; + interrupts = <91 1>; + reg-shift = <2>; + status = "disabled"; + }; + + mmuart2: serial@20102000 { + compatible = "ns16550"; + reg = <0x20102000 0x1000>; + clock-frequency = <150000000>; + current-speed = <115200>; + interrupt-parent = <&plic>; + interrupts = <92 1>; + reg-shift = <2>; + status = "disabled"; + }; + + mmuart3: serial@20104000 { + compatible = "ns16550"; + reg = <0x20104000 0x1000>; + clock-frequency = <150000000>; + current-speed = <115200>; + interrupt-parent = <&plic>; + interrupts = <93 1>; + reg-shift = <2>; + status = "disabled"; + }; + + mmuart4: serial@20106000 { + compatible = "ns16550"; + reg = <0x20106000 0x1000>; + clock-frequency = <150000000>; + current-speed = <115200>; + interrupt-parent = <&plic>; + interrupts = <94 1>; + reg-shift = <2>; + status = "disabled"; + }; + + spi0: spi@20108000 { + compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x20108000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <54 1>; + status = "disabled"; + clock-frequency = <150000000>; + }; + + spi1: spi@20109000 { + compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x20109000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <55 1>; + status = "disabled"; + clock-frequency = <150000000>; + }; + + i2c0: i2c@2010a000 { + compatible = "microchip,pic64gx-i2c", "microchip,mpfs-i2c"; + reg = <0x2010a000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <58 1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible = "microchip,pic64gx-i2c", "microchip,mpfs-i2c"; + reg = <0x2010b000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <61 1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + gpio0: gpio@20120000 { + compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; + reg = <0x20120000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <51 1>; + interrupt-controller; + #interrupt-cells = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + status = "disabled"; + }; + + gpio1: gpio@20121000 { + compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; + reg = <0x20121000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <52 1>; + interrupt-controller; + #interrupt-cells = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + status = "disabled"; + }; + + gpio2: gpio@20122000 { + compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; + reg = <0x20122000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <53 1>; + interrupt-controller; + #interrupt-cells = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + status = "disabled"; + }; + + qspi: spi@21000000 { + compatible = "microchip,pic64gx-qspi", "microchip,mpfs-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x21000000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <85 1>; + status = "disabled"; + clock-frequency = <150000000>; + }; + + syscontroller_qspi: spi@37020100 { + compatible = "microchip,pic64gx-qspi", "microchip,mpfs-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x37020100 0x1000>; + interrupt-parent = <&plic>; + interrupts = <110 1>; + status = "disabled"; + clock-frequency = <150000000>; + }; + }; +}; diff --git a/soc/microchip/pic64/CMakeLists.txt b/soc/microchip/pic64/CMakeLists.txt new file mode 100644 index 0000000000000..c11e65d03ac26 --- /dev/null +++ b/soc/microchip/pic64/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/microchip/pic64/Kconfig b/soc/microchip/pic64/Kconfig new file mode 100644 index 0000000000000..a81f7773db79f --- /dev/null +++ b/soc/microchip/pic64/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_PIC64 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_MICROCHIP_PIC64 diff --git a/soc/microchip/pic64/Kconfig.defconfig b/soc/microchip/pic64/Kconfig.defconfig new file mode 100644 index 0000000000000..de7f248e05992 --- /dev/null +++ b/soc/microchip/pic64/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_PIC64 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_MICROCHIP_PIC64 diff --git a/soc/microchip/pic64/Kconfig.soc b/soc/microchip/pic64/Kconfig.soc new file mode 100644 index 0000000000000..f50490bdffe43 --- /dev/null +++ b/soc/microchip/pic64/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_PIC64 + bool + +config SOC_FAMILY + default "microchip_pic64" if SOC_FAMILY_MICROCHIP_PIC64 + +rsource "*/Kconfig.soc" diff --git a/soc/microchip/pic64/pic64gx/CMakeLists.txt b/soc/microchip/pic64/pic64gx/CMakeLists.txt new file mode 100644 index 0000000000000..0ce57d6c5a28c --- /dev/null +++ b/soc/microchip/pic64/pic64gx/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/pic64/pic64gx/Kconfig b/soc/microchip/pic64/pic64gx/Kconfig new file mode 100644 index 0000000000000..7f6aa21d7c840 --- /dev/null +++ b/soc/microchip/pic64/pic64gx/Kconfig @@ -0,0 +1,38 @@ +# RISCV64 Microchip PIC64GX SOC configuration options + +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PIC64GX + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING + imply XIP + +config SOC_PIC64GX1000 + bool + select 64BIT + select SCHED_IPI_SUPPORTED + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING + select USE_SWITCH_SUPPORTED + select USE_SWITCH + +config SOC_PIC64GX1000_U54 + bool + select CPU_HAS_FPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_G + select RISCV_ISA_EXT_C + +config SOC_PIC64GX1000_E51 + bool + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/microchip/pic64/pic64gx/Kconfig.defconfig b/soc/microchip/pic64/pic64gx/Kconfig.defconfig new file mode 100644 index 0000000000000..78bc963eca64f --- /dev/null +++ b/soc/microchip/pic64/pic64gx/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_PIC64GX + +rsource "Kconfig.defconfig.pic64gx*" + +# PIC64GX should be configured so that the mtimer clock is 1MHz independent of the CPU clock... + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 186 + +config NUM_IRQS + default 198 + +endif # SOC_SERIES_PIC64GX diff --git a/soc/microchip/pic64/pic64gx/Kconfig.defconfig.pic64gx1000_u54 b/soc/microchip/pic64/pic64gx/Kconfig.defconfig.pic64gx1000_u54 new file mode 100644 index 0000000000000..340e17ea97cf8 --- /dev/null +++ b/soc/microchip/pic64/pic64gx/Kconfig.defconfig.pic64gx1000_u54 @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +if SOC_PIC64GX1000_U54 + +DT_COMPAT_SIFIVE_U54 := sifive,u54 + +config MP_MAX_NUM_CPUS + default $(dt_compat_enabled_num,$(DT_COMPAT_SIFIVE_U54)) + +config RV_BOOT_HART + default 1 if ($(dt_path_enabled,/cpus/cpu@1)) + default 2 if ($(dt_path_enabled,/cpus/cpu@2)) + default 3 if ($(dt_path_enabled,/cpus/cpu@3)) + default 4 if ($(dt_path_enabled,/cpus/cpu@4)) + +endif diff --git a/soc/microchip/pic64/pic64gx/Kconfig.soc b/soc/microchip/pic64/pic64gx/Kconfig.soc new file mode 100644 index 0000000000000..b9c19910490e8 --- /dev/null +++ b/soc/microchip/pic64/pic64gx/Kconfig.soc @@ -0,0 +1,28 @@ +# RISCV64 Microchip PIC64GX SOC configuration options + +# Copyright (c) 2025 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PIC64GX + bool + select SOC_FAMILY_MICROCHIP_PIC64 + help + Enable support for Microchip PIC64GX SoC. + +config SOC_PIC64GX1000 + bool + select SOC_SERIES_PIC64GX + +config SOC_PIC64GX1000_U54 + bool + select SOC_PIC64GX1000 + +config SOC_PIC64GX1000_E51 + bool + select SOC_PIC64GX1000 + +config SOC_SERIES + default "pic64gx" if SOC_SERIES_PIC64GX + +config SOC + default "pic64gx1000" if SOC_PIC64GX1000 diff --git a/soc/microchip/pic64/soc.yml b/soc/microchip/pic64/soc.yml new file mode 100644 index 0000000000000..3e7404fdf4f37 --- /dev/null +++ b/soc/microchip/pic64/soc.yml @@ -0,0 +1,9 @@ +family: +- name: microchip_pic64 + series: + - name: pic64gx + socs: + - name: pic64gx1000 + cpuclusters: + - name: e51 + - name: u54