#Verilog pipelined CPU
This is a pipelined CPU compiled in Xilinx ISE 11.4
This CPU use ipcore-memory as data and instruction memory.
Download the [ISE project] folder for the full Xilinx ISE project.
The [.bit file] folder is for the executable file that you can directly upload to your Spartan board.
Please see the pin config (at file ucf.ucf) and other source code at [.v source code] folder.

Under license GNU GPL 2.0