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MIPS32 system with 5 levels pipeline CPU
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am
audio
cpu
data_RAM
db
greybox_tmp
incremental_db
inst_RAM
keyboard
program
simulation/modelsim
vga
xck
xck_sim
.gitignore
Makefile
NJU_MIPS.asm.rpt
NJU_MIPS.cdf
NJU_MIPS.done
NJU_MIPS.eda.rpt
NJU_MIPS.fit.rpt
NJU_MIPS.fit.smsg
NJU_MIPS.fit.summary
NJU_MIPS.flow.rpt
NJU_MIPS.htm
NJU_MIPS.jdi
NJU_MIPS.map.rpt
NJU_MIPS.map.smsg
NJU_MIPS.map.summary
NJU_MIPS.pin
NJU_MIPS.qpf
NJU_MIPS.qsf
NJU_MIPS.qws
NJU_MIPS.sdc
NJU_MIPS.sld
NJU_MIPS.sof
NJU_MIPS.sta.rpt
NJU_MIPS.sta.summary
NJU_MIPS.v
NJU_MIPS_assignment_defaults.qdf
NJU_MIPS_nativelink_simulation.rpt
README.md
ascii2pcode.qip
ascii2pcode.v
ascii2pcode_bb.v
c2f.qip
c2f.v
c2f_bb.v
c5_pin_model_dump.txt
clkgen.v
data_ram_ip.qip
data_ram_ip.v
data_ram_ip_bb.v
inst_rom_ip.qip
inst_rom_ip.v
inst_rom_ip_bb.v
kb_rom.qip
kb_rom.v
kb_rom_bb.v
kb_shift_rom.qip
kb_shift_rom.v
kb_shift_rom_bb.v
macro.v
sintable.qip
sintable.v
sintable_bb.v
sopc.v
video_ram_ip0.qip
video_ram_ip0.v
video_ram_ip0_bb.v
video_ram_ip1.qip
video_ram_ip1.v
video_ram_ip1_bb.v
video_ram_ip2.qip
video_ram_ip2.v
video_ram_ip2_bb.v
video_ram_ip3.qip
video_ram_ip3.v
video_ram_ip3_bb.v
xck.bsf
xck.cmp
xck.ppf
xck.qip
xck.sip
xck.spd
xck.v
xck_sim.f

README.md

Introduction

NJU_MIPS is course project for Experimemts in Digital Logit Circuits. It is a MIPS32 system with 5 levels pipeline CPU.

Instruction

NAME FUNCTION
./hello show "Hello World"
./fib show nth fibbonaci number
./gdb step over demo programme
./mu open digital piano(cannot return)

Attributes

  • CPU Frequency : 12.5MHz
  • Align: Big Endian
  • Memory Size : 128KB
  • Instruction ROM Size : 4KB
  • Support Instruction: All supported expect ones with coprocessor and interrupt. (ll, sc is not implemented)

MMIO structure

ADDRESS DESCRIPTION FUNCTION
0x000000 - 0x003900 ROM for instruction executable; lw only
0x003900 - 0x004000 RAM for instruction executable; lw,sw only
0x004000 - 0x005000 GRAM for video readable, writable; access by vga(640*480)
0x005000 keyboard enable lb only
0x005004 keyboard ascii lb only
0x005008 audio enable wb only
- 0x006000 Reserve
0x006000 - 0x008000 RAM:Data Section
0x008000 - 0x010000 RAM:Heap

AM

AM is introduced in our ics lessons. We add MIPS32 AM to support C program. In test of AM, if succeed, you will see AC in the monitor. Otherwise, WA is shown. For now, dummy.c is tested.

Load Code

Code will be load into inst_rom from inst_rom.mif in program. You can use Makefile to generate mif file from .s file. Or you can generate mif file from binary(.data) file. Compilation may takes about 4mins.

Simulation

Modelsim Altera

Test bench is sopc_tst.v in simulation/modelsim, top module should be sopc_tst. watchreg.do helps trace all regs value in hex.

Icuras Verilog with scansion

For mac user, this lite tools is introduced. However, array variables cannot be seen.

IP Core Used

  • inst_rom_ip: 2-PORT ROM, 4096*32, inst_rom.mif
  • data_ram_ip: 2-PORT RAM, 16384*8, blank
  • ascii2pcode: 1-PORT ROM, 4096*12, a2c.mif
  • video_ram_ip0~4: 2-PORT RAM, 1024*8, vm.mif
  • kb(_shift)_rom: 1-PORT ROM, 256*8, c2a.mif
  • sintable: 1-PORT ROM, 1024*16, sintable.mif
  • c2f: 1-PORT ROM, 256*16, c2f.mif
  • xck: Altera PLL
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