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add way too much logging for memory
1 parent 58b06af commit b80fca2

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4 files changed

+132
-2
lines changed

4 files changed

+132
-2
lines changed

target/arm/cpu.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2983,4 +2983,8 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
29832983
/* Shared between translate-sve.c and sve_helper.c. */
29842984
extern const uint64_t pred_esz_masks[4];
29852985

2986+
#ifndef CONFIG_USER_ONLY
2987+
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUARMState *env);
2988+
#endif
2989+
29862990
#endif

target/arm/helper.c

Lines changed: 98 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3259,6 +3259,7 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
32593259
ARMMMUIdxBit_S1SE1 |
32603260
ARMMMUIdxBit_S1SE0);
32613261
} else {
3262+
fprintf(stderr, "Vae1is_write: pc=0x%" PRIx64 "\n", env->pc);
32623263
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
32633264
ARMMMUIdxBit_S12NSE1 |
32643265
ARMMMUIdxBit_S12NSE0);
@@ -9245,7 +9246,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
92459246
}
92469247
tbi *= 8;
92479248

9248-
/* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
9249+
/* If we are in 64-bit EL2 or EL3 then there is no 1, so mark it
92499250
* invalid.
92509251
*/
92519252
if (el > 1) {
@@ -10316,7 +10317,7 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
1031610317
* @fi: set to fault info if the translation fails
1031710318
* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
1031810319
*/
10319-
static bool get_phys_addr(CPUARMState *env, target_ulong address,
10320+
static bool get_phys_addr_real(CPUARMState *env, target_ulong address,
1032010321
MMUAccessType access_type, ARMMMUIdx mmu_idx,
1032110322
hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
1032210323
target_ulong *page_size,
@@ -10437,6 +10438,25 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
1043710438
}
1043810439
}
1043910440

10441+
static bool chatty = true;
10442+
10443+
static bool get_phys_addr(CPUARMState *env, target_ulong address,
10444+
MMUAccessType access_type, ARMMMUIdx mmu_idx,
10445+
hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
10446+
target_ulong *page_size,
10447+
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
10448+
{
10449+
if (chatty) {
10450+
fprintf(stderr, "Get phys addr: 0x%" PRIx64 " %x %x\n", address, access_type, mmu_idx);
10451+
}
10452+
bool retval = get_phys_addr_real(env, address, access_type, mmu_idx, phys_ptr,
10453+
attrs, prot, page_size, fi, cacheattrs);
10454+
if (chatty) {
10455+
fprintf(stderr, "Retval: %s phys 0x%" PRIx64 " prot %x type %x\n", retval? "true": "false", *phys_ptr, *prot, fi->type);
10456+
}
10457+
return retval;
10458+
}
10459+
1044010460
/* Walk the page table and (if the mapping exists) add the page
1044110461
* to the TLB. Return false on success, or true on failure. Populate
1044210462
* fsr with ARM DFSR/IFSR fault register format value on failure.
@@ -12430,3 +12450,79 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
1243012450
*pflags = flags;
1243112451
*cs_base = 0;
1243212452
}
12453+
12454+
#ifndef CONFIG_USER_ONLY
12455+
12456+
static void dump_mmu_lpae(FILE *f, fprintf_function cpu_fprintf, CPUARMState *env, ARMMMUIdx mmu_idx) {
12457+
//uint64_t ttbr = regime_ttbr(env, mmu_idx, 1);
12458+
//hwaddr descaddr = extract64(ttbr, 0, 48);
12459+
// https://developer.arm.com/products/architecture/a-profile/docs/100940/latest/translation-tables-in-armv8-a
12460+
//cpu_physical_memory_read()
12461+
}
12462+
12463+
hwaddr arm_cpu_get_phys_page_attrs_memdump(CPUState *cs, vaddr addr,
12464+
MemTxAttrs *attrs, int* protOut, ARMCacheAttrs* cacheAttrsOut)
12465+
{
12466+
ARMCPU *cpu = ARM_CPU(cs);
12467+
CPUARMState *env = &cpu->env;
12468+
hwaddr phys_addr;
12469+
target_ulong page_size;
12470+
int prot;
12471+
bool ret;
12472+
ARMMMUFaultInfo fi = {};
12473+
ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
12474+
12475+
*attrs = (MemTxAttrs) {};
12476+
12477+
ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
12478+
attrs, &prot, &page_size, &fi, cacheAttrsOut);
12479+
12480+
if (ret) {
12481+
return -1;
12482+
}
12483+
*protOut = prot;
12484+
return phys_addr;
12485+
}
12486+
12487+
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUARMState *env) {
12488+
/*ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
12489+
if (regime_translation_disabled(env, mmu_idx)) {
12490+
cpu_fprintf(f, "MMU disabled\n");
12491+
return;
12492+
}
12493+
if (!regime_using_lpae_format(env, mmu_idx)) {
12494+
cpu_fprintf(f, "MMU not in LPAE mode; printing mappings not implemented");
12495+
return;
12496+
}
12497+
dump_mmu_lpae(f, cpu_fprintf, env, mmu_idx);*/
12498+
chatty = false;
12499+
cpu_fprintf(f, "what\n");
12500+
uint64_t lastPhysAddr = 0x1;
12501+
uint64_t lastVirtAddr = 0x0;
12502+
int lastProt = 0;
12503+
uint64_t addr;
12504+
CPUState *cs = ENV_GET_CPU(env);
12505+
ARMCacheAttrs lastCacheAttrs = {};
12506+
for (addr = 0xffffffe000000000ull; addr < 0xffffffff00000000ull; addr += 0x10000) {
12507+
MemTxAttrs attrs = {};
12508+
int prot = lastProt;
12509+
ARMCacheAttrs cacheAttrs = lastCacheAttrs;
12510+
hwaddr phys_addr = arm_cpu_get_phys_page_attrs_memdump(cs, addr, &attrs, &prot, &cacheAttrs);
12511+
if (phys_addr != lastPhysAddr + 0x10000 || prot != lastProt || cacheAttrs.attrs != lastCacheAttrs.attrs || cacheAttrs.shareability != lastCacheAttrs.shareability) {
12512+
if (lastPhysAddr != ~0) {
12513+
cpu_fprintf(f, "0x%" PRIx64 "-0x%" PRIx64 ": 0x%" PRIx64 " %x %x %x\n",
12514+
lastVirtAddr, addr, lastPhysAddr, lastProt, lastCacheAttrs.attrs, lastCacheAttrs.shareability);
12515+
}
12516+
lastVirtAddr = addr;
12517+
lastPhysAddr = phys_addr;
12518+
lastProt = prot;
12519+
lastCacheAttrs = cacheAttrs;
12520+
}
12521+
}
12522+
if (lastPhysAddr != ~0) {
12523+
cpu_fprintf(f, "0x%" PRIx64 "-0x%" PRIx64 ": 0x%" PRIx64 " %x %x %x\n",
12524+
lastVirtAddr, addr, lastPhysAddr, lastProt, lastCacheAttrs.attrs, lastCacheAttrs.shareability);
12525+
}
12526+
chatty = true;
12527+
}
12528+
#endif

target/arm/monitor.c

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,9 @@
2424
#include "hw/boards.h"
2525
#include "kvm_arm.h"
2626
#include "qapi/qapi-commands-misc.h"
27+
#include "monitor/monitor.h"
28+
#include "monitor/hmp-target.h"
29+
#include "exec/exec-all.h"
2730

2831
static GICCapability *gic_cap_new(int version)
2932
{
@@ -82,3 +85,28 @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
8285

8386
return head;
8487
}
88+
89+
void hmp_info_mem(Monitor *mon, const QDict *qdict)
90+
{
91+
CPUArchState *env;
92+
93+
env = mon_get_cpu_env();
94+
if (!env) {
95+
monitor_printf(mon, "No CPU available\n");
96+
return;
97+
}
98+
dump_mmu((FILE *)mon, (fprintf_function)monitor_printf, env);
99+
}
100+
101+
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
102+
{
103+
CPUArchState *env;
104+
105+
env = mon_get_cpu_env();
106+
if (!env) {
107+
monitor_printf(mon, "No CPU available\n");
108+
return;
109+
}
110+
tlb_flush(CPU(arm_env_get_cpu(env)));
111+
monitor_printf(mon, "tlb flushed\n");
112+
}

target/arm/translate-a64.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,8 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
176176
cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
177177
vfp_get_fpcr(env), vfp_get_fpsr(env));
178178
}
179+
cpu_fprintf(f, "TTBR0_EL1=%016" PRIx64 " TTBR1_EL1=%016" PRIx64"\n",
180+
env->cp15.ttbr0_el[1], env->cp15.ttbr1_el[1]);
179181
}
180182

181183
void gen_a64_set_pc_im(uint64_t val)

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