@@ -3259,6 +3259,7 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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ARMMMUIdxBit_S1SE1 |
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ARMMMUIdxBit_S1SE0 );
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} else {
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+ fprintf (stderr , "Vae1is_write: pc=0x%" PRIx64 "\n" , env -> pc );
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tlb_flush_page_by_mmuidx_all_cpus_synced (cs , pageaddr ,
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ARMMMUIdxBit_S12NSE1 |
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ARMMMUIdxBit_S12NSE0 );
@@ -9245,7 +9246,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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}
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tbi *= 8 ;
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- /* If we are in 64-bit EL2 or EL3 then there is no TTBR1 , so mark it
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+ /* If we are in 64-bit EL2 or EL3 then there is no 1 , so mark it
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* invalid.
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*/
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if (el > 1 ) {
@@ -10316,7 +10317,7 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
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* @fi: set to fault info if the translation fails
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* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
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*/
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- static bool get_phys_addr (CPUARMState * env , target_ulong address ,
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+ static bool get_phys_addr_real (CPUARMState * env , target_ulong address ,
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MMUAccessType access_type , ARMMMUIdx mmu_idx ,
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hwaddr * phys_ptr , MemTxAttrs * attrs , int * prot ,
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target_ulong * page_size ,
@@ -10437,6 +10438,25 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
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}
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}
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+ static bool chatty = true;
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+
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+ static bool get_phys_addr (CPUARMState * env , target_ulong address ,
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+ MMUAccessType access_type , ARMMMUIdx mmu_idx ,
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+ hwaddr * phys_ptr , MemTxAttrs * attrs , int * prot ,
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+ target_ulong * page_size ,
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+ ARMMMUFaultInfo * fi , ARMCacheAttrs * cacheattrs )
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+ {
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+ if (chatty ) {
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+ fprintf (stderr , "Get phys addr: 0x%" PRIx64 " %x %x\n" , address , access_type , mmu_idx );
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+ }
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+ bool retval = get_phys_addr_real (env , address , access_type , mmu_idx , phys_ptr ,
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+ attrs , prot , page_size , fi , cacheattrs );
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+ if (chatty ) {
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+ fprintf (stderr , "Retval: %s phys 0x%" PRIx64 " prot %x type %x\n" , retval ? "true" : "false" , * phys_ptr , * prot , fi -> type );
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+ }
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+ return retval ;
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+ }
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+
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/* Walk the page table and (if the mapping exists) add the page
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* to the TLB. Return false on success, or true on failure. Populate
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* fsr with ARM DFSR/IFSR fault register format value on failure.
@@ -12430,3 +12450,79 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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* pflags = flags ;
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* cs_base = 0 ;
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}
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+
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+ #ifndef CONFIG_USER_ONLY
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+
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+ static void dump_mmu_lpae (FILE * f , fprintf_function cpu_fprintf , CPUARMState * env , ARMMMUIdx mmu_idx ) {
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+ //uint64_t ttbr = regime_ttbr(env, mmu_idx, 1);
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+ //hwaddr descaddr = extract64(ttbr, 0, 48);
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+ // https://developer.arm.com/products/architecture/a-profile/docs/100940/latest/translation-tables-in-armv8-a
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+ //cpu_physical_memory_read()
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+ }
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+
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+ hwaddr arm_cpu_get_phys_page_attrs_memdump (CPUState * cs , vaddr addr ,
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+ MemTxAttrs * attrs , int * protOut , ARMCacheAttrs * cacheAttrsOut )
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+ {
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+ ARMCPU * cpu = ARM_CPU (cs );
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+ CPUARMState * env = & cpu -> env ;
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+ hwaddr phys_addr ;
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+ target_ulong page_size ;
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+ int prot ;
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+ bool ret ;
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+ ARMMMUFaultInfo fi = {};
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+ ARMMMUIdx mmu_idx = core_to_arm_mmu_idx (env , cpu_mmu_index (env , false));
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+
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+ * attrs = (MemTxAttrs ) {};
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+
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+ ret = get_phys_addr (env , addr , 0 , mmu_idx , & phys_addr ,
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+ attrs , & prot , & page_size , & fi , cacheAttrsOut );
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+
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+ if (ret ) {
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+ return -1 ;
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+ }
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+ * protOut = prot ;
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+ return phys_addr ;
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+ }
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+
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+ void dump_mmu (FILE * f , fprintf_function cpu_fprintf , CPUARMState * env ) {
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+ /*ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
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+ if (regime_translation_disabled(env, mmu_idx)) {
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+ cpu_fprintf(f, "MMU disabled\n");
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+ return;
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+ }
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+ if (!regime_using_lpae_format(env, mmu_idx)) {
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+ cpu_fprintf(f, "MMU not in LPAE mode; printing mappings not implemented");
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+ return;
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+ }
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+ dump_mmu_lpae(f, cpu_fprintf, env, mmu_idx);*/
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+ chatty = false;
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+ cpu_fprintf (f , "what\n" );
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+ uint64_t lastPhysAddr = 0x1 ;
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+ uint64_t lastVirtAddr = 0x0 ;
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+ int lastProt = 0 ;
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+ uint64_t addr ;
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+ CPUState * cs = ENV_GET_CPU (env );
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+ ARMCacheAttrs lastCacheAttrs = {};
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+ for (addr = 0xffffffe000000000ull ; addr < 0xffffffff00000000ull ; addr += 0x10000 ) {
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+ MemTxAttrs attrs = {};
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+ int prot = lastProt ;
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+ ARMCacheAttrs cacheAttrs = lastCacheAttrs ;
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+ hwaddr phys_addr = arm_cpu_get_phys_page_attrs_memdump (cs , addr , & attrs , & prot , & cacheAttrs );
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+ if (phys_addr != lastPhysAddr + 0x10000 || prot != lastProt || cacheAttrs .attrs != lastCacheAttrs .attrs || cacheAttrs .shareability != lastCacheAttrs .shareability ) {
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+ if (lastPhysAddr != ~0 ) {
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+ cpu_fprintf (f , "0x%" PRIx64 "-0x%" PRIx64 ": 0x%" PRIx64 " %x %x %x\n" ,
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+ lastVirtAddr , addr , lastPhysAddr , lastProt , lastCacheAttrs .attrs , lastCacheAttrs .shareability );
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+ }
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+ lastVirtAddr = addr ;
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+ lastPhysAddr = phys_addr ;
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+ lastProt = prot ;
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+ lastCacheAttrs = cacheAttrs ;
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+ }
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+ }
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+ if (lastPhysAddr != ~0 ) {
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+ cpu_fprintf (f , "0x%" PRIx64 "-0x%" PRIx64 ": 0x%" PRIx64 " %x %x %x\n" ,
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+ lastVirtAddr , addr , lastPhysAddr , lastProt , lastCacheAttrs .attrs , lastCacheAttrs .shareability );
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+ }
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+ chatty = true;
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+ }
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+ #endif
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