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RISC-V behavior tests disabled #3338

@andrewrk

Description

@andrewrk

These are all upstream issues with LLVM.

@newStackCall causes:

LLVM ERROR: Named registers not implemented for this target

Issues with f16:

LLVM ERROR: Cannot select: 0x39d32ee0: f32,ch = load<(dereferenceable load 2 from %ir.a), anyext from f16> 0x39d29678, FrameIndex:i64<0>, undef:i64, widening.zig:23:18
  0x39d1aa68: i64 = FrameIndex<0>
  0x38d69710: i64 = undef
In function: behavior.widening.test "float widening"
LLVM ERROR: Cannot select: 0x393500f8: f32 = fp16_to_fp Constant:i64<18988>, widening.zig:40:19
  0x39350298: i64 = Constant<18988>
In function: behavior.widening.test "float widening f16 to f128"

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    arch-riscv6464-bit RISC-VbugObserved behavior contradicts documented or intended behaviorcontributor friendlyThis issue is limited in scope and/or knowledge of Zig internals.upstreamAn issue with a third party project that Zig uses.

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