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ISPC release with long-awaited function templates technical preview; new hardware support for 4th generation Intel® Xeon® Scalable (codename Sapphire Rapids) CPUs, Intel® Data Center GPU Max (codename Ponte Vecchio), and updated support for Intel® Arc™ GPUs; improved performance and compile time; an enhanced ISPC Runtime; a bunch of stability fixes and more. The release is based on patched LLVM 14.0.6.
Language changes:
Function templates support was introduced in ISPC and it's currently in technical preview, meaning that current language definition might change in future versions. For more details please refer to Function Templates section of documentation.
ISPC has got several other language changes needed for ISPC/SYCL interoperability (an experimental feature):
Support of __regcall attribute.
A new language construct invoke_sycl which is used to call SYCL function from ISPC. The function must be declared on ISPC side with extern "SYCL" __regcall qualifiers.
Support of extern "C" functions definitions.
New hardware support:
Targets for 4th generation Intel® Xeon® Scalable (codename Sapphire Rapids) CPUs were introduced: avx512spr-x4, avx512spr-x8,avx512spr-x16, avx512spr-x32, avx512spr-x64. The key difference with other AVX512 targets is native support for FP16.
New xehpc-x16/xehpc-x32 targets were added for Intel® Data Center GPU Max (codename Ponte Vecchio). A new pvc device name was introduced.
New device names acm-g10, acm-g11, and acm-g12 were added for Intel® Arc™ Graphics. The dg2 device name has been removed.
Support for Aarch64 targets was enabled on Windows.
ISPC Runtime:
A chunking allocator was introduced that can be enabled with ISPCRT_MEM_POOL (see details are here).
An API was added to link input modules through ispcrtStaticLinkModules (using linking on vISA level under the hood) and ispcrtDynamicLinkModules (using binary linking under the hood).
Support for creating multiple devices within a single context was added, and an API was added to get a function pointer from a module. It's also possible to construct ISPC RT objects from native handlers now.
ISPC RT verbose mode was added that can be enabled through ISPCRT_VERBOSE.
Performance:
There's a significant performance boost on Xe targets caused by updates in the ISPC optimization pipeline and the usage of the new spill-cost IGC finalizer function, which dramatically reduces spill size.
Utilities:
ISPC link mode has been introduced, allowing to link several LLVM bitcode or SPIR-V files and output the result as LLVM bitcode or SPIR-V. For example:
ispc link test_a.bc test_b.bc --emit-spirv -o test.spv
CMake utilities was improved, and support was added for building an ISPC GPU target from multiple ISPC files, linking them with ispc --link. An application's ISPC CMakeLists would look like this:
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ISPC release with long-awaited function templates technical preview; new hardware support for 4th generation Intel® Xeon® Scalable (codename Sapphire Rapids) CPUs, Intel® Data Center GPU Max (codename Ponte Vecchio), and updated support for Intel® Arc™ GPUs; improved performance and compile time; an enhanced ISPC Runtime; a bunch of stability fixes and more. The release is based on patched LLVM 14.0.6.
Language changes:
Function templates support was introduced in ISPC and it's currently in technical preview, meaning that current language definition might change in future versions. For more details please refer to Function Templates section of documentation.
ISPC has got several other language changes needed for ISPC/SYCL interoperability (an experimental feature):
__regcall
attribute.invoke_sycl
which is used to call SYCL function from ISPC. The function must be declared on ISPC side withextern "SYCL" __regcall
qualifiers.extern "C"
functions definitions.New hardware support:
avx512spr-x4
,avx512spr-x8
,avx512spr-x16
,avx512spr-x32
,avx512spr-x64
. The key difference with other AVX512 targets is native support for FP16.xehpc-x16
/xehpc-x32
targets were added for Intel® Data Center GPU Max (codename Ponte Vecchio). A newpvc
device name was introduced.acm-g10
,acm-g11
, andacm-g12
were added for Intel® Arc™ Graphics. Thedg2
device name has been removed.ISPC Runtime:
ISPCRT_MEM_POOL
(see details are here).ispcrtStaticLinkModules
(using linking on vISA level under the hood) andispcrtDynamicLinkModules
(using binary linking under the hood).ISPCRT_VERBOSE
.Performance:
There's a significant performance boost on Xe targets caused by updates in the ISPC optimization pipeline and the usage of the new spill-cost IGC finalizer function, which dramatically reduces spill size.
Utilities:
link
mode has been introduced, allowing to link several LLVM bitcode or SPIR-V files and output the result as LLVM bitcode or SPIR-V. For example:ispc --link
. An application's ISPC CMakeLists would look like this:Runtime Dependencies when targeting GPU:
Linux:
Windows:
Components revisions used in GPU-enabled build:
This discussion was created from the release === v1.19.0 === (28 February 2023).
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