Náčrtky a bloková schémata pro (mikro)procesory do předmětu HAW a nejen
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Updated
May 31, 2024 - TeX
Náčrtky a bloková schémata pro (mikro)procesory do předmětu HAW a nejen
high instruction-level-parallelism (ILP) using Resource-Flow-Execution
This repository contains the technical documentation of the prototype station for pre-cleaning of the HDPE bottles. The station aims to provide a sustainable solution for enhancing the recycling processes in low-resource settings.
Design and Development of AES Encryption and Decryption Modules in Verilog HDL for AES128, AES192, and AES256 Algorithms.
介绍和罗列关于硬件设计所需要考虑的各个方面。纯个人经验总结,非科班念经。永远地不定期更新。CC-BY-NC-SA 4.0。
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
KiCad project and OpenSCAD model for a custom NeoPixel ring which uses a USB-C socket to interface with LEDswarm controller mainboards.
Robust SystemVerilog Linter and Formatter to enhance code quality and ensure standards compliance. Perfect for hardware designers seeking efficient verification and readable code.
RISCV processor done in both single cycle and pipeline (with CSR support) form.
A hardware component library developed with ROHD.
STM32 Pocket Game/Dev Console 🕹️ is a handheld device powered by 2xAAA batteries. It features 5 programmable buttons, 2 LEDs, and an SPI TFT 2.4" display with a resolution of 320x240 pixels.
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
This repository contains an HPC (High Performance Computing) reliability benchmark, carrying out fault injection experiments on a variety of HPC applications, targeting BLAS (Basic Linear Algebra Subroutines) GEMM (GEneral Matrix Multiply) operations.
preamplifier & power distributor for instruments
A custom 16-bit processor with a custom assembly language and emulator, based off of the ARM 32-bit processor.
Hardware-Scheduled Pipeline Processor in VHDL
Instruction Set Architecture and pipeline to implement a new operation in the computer hardware.
hardware design of universal NPU(CNN accelerator) for various convolution neural network
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