Pinned Loading
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SONY-Cell-SPU-Processor
SONY-Cell-SPU-Processor PublicThis repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) o…
Verilog 15
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FPGA-Note-Tuner
FPGA-Note-Tuner PublicThis project involves designing a guitar tuner using an Artix-7 FPGA from Xilinx. The tuner processes 24-bit, 48 kHz stereo audio input, performs Fast Fourier Transform (FFT) to analyze frequencies…
VHDL
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SIMD_Multimedia_Processing_Unit
SIMD_Multimedia_Processing_Unit PublicThis project involves the design and implementation of a 4-stage pipelined multimedia processing unit using VHDL/Verilog hardware description languages.
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Posit-cpp
Posit-cpp PublicC++ library is specifically designed to facilitate the implementation and evaluation of the posit number system, a new alternative to floating-point arithmetic that offers improved accuracy, perfor…
C++
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Fiduccia-Mattheyses-partitioning
Fiduccia-Mattheyses-partitioning PublicTo implement and experiment the Fiduccia-Mattheyses partitioning algorithm for gate-level designs.
Raku
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