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| 1 | +# Copyright (c) 2019 Alex Forencich |
| 2 | +# |
| 3 | +# Permission is hereby granted, free of charge, to any person obtaining a copy |
| 4 | +# of this software and associated documentation files (the "Software"), to deal |
| 5 | +# in the Software without restriction, including without limitation the rights |
| 6 | +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 7 | +# copies of the Software, and to permit persons to whom the Software is |
| 8 | +# furnished to do so, subject to the following conditions: |
| 9 | +# |
| 10 | +# The above copyright notice and this permission notice shall be included in |
| 11 | +# all copies or substantial portions of the Software. |
| 12 | +# |
| 13 | +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY |
| 15 | +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 16 | +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 17 | +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 18 | +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 19 | +# THE SOFTWARE. |
| 20 | + |
| 21 | +# AXI stream asynchronous FIFO timing constraints |
| 22 | + |
| 23 | +foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo || REF_NAME == axis_async_fifo)}] { |
| 24 | + puts "Inserting timing constraints for axis_async_fifo instance $fifo_inst" |
| 25 | + |
| 26 | + # get clock periods |
| 27 | + set read_clk [get_clocks -of_objects [get_pins $fifo_inst/rd_ptr_reg_reg[0]/C]] |
| 28 | + set write_clk [get_clocks -of_objects [get_pins $fifo_inst/wr_ptr_reg_reg[0]/C]] |
| 29 | + |
| 30 | + set read_clk_period [get_property -min PERIOD $read_clk] |
| 31 | + set write_clk_period [get_property -min PERIOD $write_clk] |
| 32 | + |
| 33 | + set min_clk_period [expr $read_clk_period < $write_clk_period ? $read_clk_period : $write_clk_period] |
| 34 | + |
| 35 | + # reset synchronization |
| 36 | + set reset_ffs [get_cells -hier -regexp ".*/(s|m)_rst_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] |
| 37 | + |
| 38 | + set_property ASYNC_REG TRUE $reset_ffs |
| 39 | + set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}] |
| 40 | + |
| 41 | + set_false_path -to [get_pins $fifo_inst/s_rst_sync2_reg_reg/D] |
| 42 | + set_max_delay -from [get_cells $fifo_inst/s_rst_sync2_reg_reg] -to [get_cells $fifo_inst/s_rst_sync3_reg_reg] $min_clk_period |
| 43 | + |
| 44 | + set_false_path -to [get_pins $fifo_inst/m_rst_sync2_reg_reg/D] |
| 45 | + set_max_delay -from [get_cells $fifo_inst/m_rst_sync2_reg_reg] -to [get_cells $fifo_inst/m_rst_sync3_reg_reg] $min_clk_period |
| 46 | + |
| 47 | + # pointer synchronization |
| 48 | + set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/(wr|rd)_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"] |
| 49 | + |
| 50 | + set_max_delay -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $fifo_inst/rd_ptr_gray_sync1_reg_reg[*]] -datapath_only $read_clk_period |
| 51 | + set_bus_skew -from [get_cells "$fifo_inst/rd_ptr_reg_reg[*] $fifo_inst/rd_ptr_gray_reg_reg[*]"] -to [get_cells $fifo_inst/rd_ptr_gray_sync1_reg_reg[*]] $write_clk_period |
| 52 | + set_max_delay -from [get_cells "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_sync_gray_reg_reg[*]"] -to [get_cells $fifo_inst/wr_ptr_gray_sync1_reg_reg[*]] -datapath_only $write_clk_period |
| 53 | + set_bus_skew -from [get_cells "$fifo_inst/wr_ptr_reg_reg[*] $fifo_inst/wr_ptr_gray_reg_reg[*] $fifo_inst/wr_ptr_sync_gray_reg_reg[*]"] -to [get_cells $fifo_inst/wr_ptr_gray_sync1_reg_reg[*]] $read_clk_period |
| 54 | + |
| 55 | + # frame FIFO pointer update synchronization |
| 56 | + set update_ffs [get_cells -hier -regexp ".*/wr_ptr_update(_ack)?_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] |
| 57 | + |
| 58 | + if {[llength $update_ffs]} { |
| 59 | + set_property ASYNC_REG TRUE $update_ffs |
| 60 | + |
| 61 | + set_max_delay -from [get_cells $fifo_inst/wr_ptr_update_reg_reg] -to [get_cells $fifo_inst/wr_ptr_update_sync1_reg_reg] -datapath_only $write_clk_period |
| 62 | + set_max_delay -from [get_cells $fifo_inst/wr_ptr_update_sync3_reg_reg] -to [get_cells $fifo_inst/wr_ptr_update_ack_sync1_reg_reg] -datapath_only $read_clk_period |
| 63 | + } |
| 64 | + |
| 65 | + # status synchronization |
| 66 | + foreach i {overflow bad_frame good_frame} { |
| 67 | + set status_sync_regs [get_cells -quiet -hier -regexp ".*/${i}_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] |
| 68 | + |
| 69 | + if {[llength $status_sync_regs]} { |
| 70 | + set_property ASYNC_REG TRUE $status_sync_regs |
| 71 | + |
| 72 | + set_max_delay -from [get_cells $fifo_inst/${i}_sync1_reg_reg] -to [get_cells $fifo_inst/${i}_sync2_reg_reg] -datapath_only $read_clk_period |
| 73 | + } |
| 74 | + } |
| 75 | +} |
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