@@ -33,19 +33,19 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo ||
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set min_clk_period [expr $read_clk_period < $write_clk_period ? $read_clk_period : $write_clk_period ]
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# reset synchronization
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- set reset_ffs [get_cells -hier -regexp " .*/(s|m)_rst_sync\[ 123\] _reg_reg" -filter " PARENT == $fifo_inst " ]
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+ set reset_ffs [get_cells -quiet - hier -regexp " .*/(s|m)_rst_sync\[ 123\] _reg_reg" -filter " PARENT == $fifo_inst " ]
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if {[llength $reset_ffs ]} {
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set_property ASYNC_REG TRUE $reset_ffs
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set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
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}
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- if {[llength [get_cells $fifo_inst /s_rst_sync2_reg_reg]]} {
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+ if {[llength [get_cells -quiet $fifo_inst /s_rst_sync2_reg_reg]]} {
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set_false_path -to [get_pins $fifo_inst /s_rst_sync2_reg_reg/D]
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set_max_delay -from [get_cells $fifo_inst /s_rst_sync2_reg_reg] -to [get_cells $fifo_inst /s_rst_sync3_reg_reg] $min_clk_period
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}
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- if {[llength [get_cells $fifo_inst /m_rst_sync2_reg_reg]]} {
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+ if {[llength [get_cells -quiet $fifo_inst /m_rst_sync2_reg_reg]]} {
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set_false_path -to [get_pins $fifo_inst /m_rst_sync2_reg_reg/D]
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set_max_delay -from [get_cells $fifo_inst /m_rst_sync2_reg_reg] -to [get_cells $fifo_inst /m_rst_sync3_reg_reg] $min_clk_period
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}
@@ -55,11 +55,11 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo ||
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set_max_delay -from [get_cells " $fifo_inst /rd_ptr_reg_reg[ *] $fifo_inst /rd_ptr_gray_reg_reg[ *] " ] -to [get_cells $fifo_inst /rd_ptr_gray_sync1_reg_reg[*]] -datapath_only $read_clk_period
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set_bus_skew -from [get_cells " $fifo_inst /rd_ptr_reg_reg[ *] $fifo_inst /rd_ptr_gray_reg_reg[ *] " ] -to [get_cells $fifo_inst /rd_ptr_gray_sync1_reg_reg[*]] $write_clk_period
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- set_max_delay -from [get_cells " $fifo_inst /wr_ptr_reg_reg[ *] $fifo_inst /wr_ptr_gray_reg_reg[ *] $fifo_inst /wr_ptr_sync_gray_reg_reg[ *] " ] -to [get_cells $fifo_inst /wr_ptr_gray_sync1_reg_reg[*]] -datapath_only $write_clk_period
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- set_bus_skew -from [get_cells " $fifo_inst /wr_ptr_reg_reg[ *] $fifo_inst /wr_ptr_gray_reg_reg[ *] $fifo_inst /wr_ptr_sync_gray_reg_reg[ *] " ] -to [get_cells $fifo_inst /wr_ptr_gray_sync1_reg_reg[*]] $read_clk_period
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+ set_max_delay -from [get_cells -quiet " $fifo_inst /wr_ptr_reg_reg[ *] $fifo_inst /wr_ptr_gray_reg_reg[ *] $fifo_inst /wr_ptr_sync_gray_reg_reg[ *] " ] -to [get_cells $fifo_inst /wr_ptr_gray_sync1_reg_reg[*]] -datapath_only $write_clk_period
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+ set_bus_skew -from [get_cells -quiet " $fifo_inst /wr_ptr_reg_reg[ *] $fifo_inst /wr_ptr_gray_reg_reg[ *] $fifo_inst /wr_ptr_sync_gray_reg_reg[ *] " ] -to [get_cells $fifo_inst /wr_ptr_gray_sync1_reg_reg[*]] $read_clk_period
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# frame FIFO pointer update synchronization
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- set update_ffs [get_cells -hier -regexp " .*/wr_ptr_update(_ack)?_sync\[ 123\] _reg_reg" -filter " PARENT == $fifo_inst " ]
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+ set update_ffs [get_cells -quiet - hier -regexp " .*/wr_ptr_update(_ack)?_sync\[ 123\] _reg_reg" -filter " PARENT == $fifo_inst " ]
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if {[llength $update_ffs ]} {
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set_property ASYNC_REG TRUE $update_ffs
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