Fix AXI stream async frame FIFO write pointer synchronization

Author: alexforencich

rtl/axis_async_fifo.v

@@ -124,6 +124,7 @@ localparam WIDTH       = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
 reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
 reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
 reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
+reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_sync_gray_next;
 reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_gray_next;
 reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
@@ -135,6 +136,14 @@ reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
 reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
 
+reg wr_ptr_update_valid_reg = 1'b0, wr_ptr_update_valid_next;
+reg wr_ptr_update_reg = 1'b0, wr_ptr_update_next;
+reg wr_ptr_update_sync1_reg = 1'b0;
+reg wr_ptr_update_sync2_reg = 1'b0;
+reg wr_ptr_update_sync3_reg = 1'b0;
+reg wr_ptr_update_ack_sync1_reg = 1'b0;
+reg wr_ptr_update_ack_sync2_reg = 1'b0;
+
 reg s_rst_sync1_reg = 1'b1;
 reg s_rst_sync2_reg = 1'b1;
 reg s_rst_sync3_reg = 1'b1;
@@ -160,7 +169,7 @@ wire full_cur = ((wr_ptr_cur_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_
                  (wr_ptr_cur_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
                  (wr_ptr_cur_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
 // empty when pointers match exactly
-wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
+wire empty = rd_ptr_gray_reg == (FRAME_FIFO ? wr_ptr_gray_sync1_reg : wr_ptr_gray_sync2_reg);
 // overflow within packet
 wire full_wr = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) &&
                 (wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0]));
@@ -253,8 +262,22 @@ always @* begin
     wr_ptr_next = wr_ptr_reg;
     wr_ptr_cur_next = wr_ptr_cur_reg;
     wr_ptr_gray_next = wr_ptr_gray_reg;
+    wr_ptr_sync_gray_next = wr_ptr_sync_gray_reg;
     wr_ptr_cur_gray_next = wr_ptr_cur_gray_reg;
 
+    wr_ptr_update_valid_next = wr_ptr_update_valid_reg;
+    wr_ptr_update_next = wr_ptr_update_reg;
+
+    if (FRAME_FIFO && wr_ptr_update_valid_reg) begin
+        // have updated pointer to sync
+        if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin
+            // no sync in progress; sync update
+            wr_ptr_update_valid_next = 1'b0;
+            wr_ptr_sync_gray_next = wr_ptr_gray_reg;
+            wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg;
+        end
+    end
+
     if (s_axis_tready && s_axis_tvalid) begin
         // transfer in
         if (!FRAME_FIFO) begin
@@ -288,6 +311,17 @@ always @* begin
                     // good packet, update write pointer
                     wr_ptr_next = wr_ptr_cur_reg + 1;
                     wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
+
+                    if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin
+                        // no sync in progress; sync update
+                        wr_ptr_update_valid_next = 1'b0;
+                        wr_ptr_sync_gray_next = wr_ptr_gray_next;
+                        wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg;
+                    end else begin
+                        // sync in progress; flag it for later
+                        wr_ptr_update_valid_next = 1'b1;
+                    end
+
                     good_frame_next = 1'b1;
                 end
             end
@@ -300,8 +334,12 @@ always @(posedge s_clk) begin
         wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
         wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
         wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
+        wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}};
         wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}};
 
+        wr_ptr_update_valid_reg <= 1'b0;
+        wr_ptr_update_reg <= 1'b0;
+
         drop_frame_reg <= 1'b0;
         overflow_reg <= 1'b0;
         bad_frame_reg <= 1'b0;
@@ -310,8 +348,12 @@ always @(posedge s_clk) begin
         wr_ptr_reg <= wr_ptr_next;
         wr_ptr_cur_reg <= wr_ptr_cur_next;
         wr_ptr_gray_reg <= wr_ptr_gray_next;
+        wr_ptr_sync_gray_reg <= wr_ptr_sync_gray_next;
         wr_ptr_cur_gray_reg <= wr_ptr_cur_gray_next;
 
+        wr_ptr_update_valid_reg <= wr_ptr_update_valid_next;
+        wr_ptr_update_reg <= wr_ptr_update_next;
+
         drop_frame_reg <= drop_frame_next;
         overflow_reg <= overflow_next;
         bad_frame_reg <= bad_frame_next;
@@ -334,19 +376,33 @@ always @(posedge s_clk) begin
     if (s_rst_sync3_reg) begin
         rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
         rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
+        wr_ptr_update_ack_sync1_reg <= 1'b0;
+        wr_ptr_update_ack_sync2_reg <= 1'b0;
     end else begin
         rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
         rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
+        wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
+        wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
     end
 end
 
 always @(posedge m_clk) begin
     if (m_rst_sync3_reg) begin
         wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
         wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
+        wr_ptr_update_sync1_reg <= 1'b0;
+        wr_ptr_update_sync2_reg <= 1'b0;
+        wr_ptr_update_sync3_reg <= 1'b0;
     end else begin
-        wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
+        if (!FRAME_FIFO) begin
+            wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
+        end else if (wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin
+            wr_ptr_gray_sync1_reg <= wr_ptr_sync_gray_reg;
+        end
         wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
+        wr_ptr_update_sync1_reg <= wr_ptr_update_reg;
+        wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
+        wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
     end
 end