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alexforencichalexforencich
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Include instance names in error messages
1 parent 0a85a4a commit ce00df8

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7 files changed

+22
-22
lines changed

7 files changed

+22
-22
lines changed

‎rtl/axis_adapter.v

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -109,17 +109,17 @@ parameter SEGMENT_KEEP_WIDTH = KEEP_WIDTH / SEGMENT_COUNT;
109109
// bus width assertions
110110
initial begin
111111
if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
112-
$error("Error: input data width not evenly divisble");
112+
$error("Error: input data width not evenly divisble (instance %m)");
113113
$finish;
114114
end
115115

116116
if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
117-
$error("Error: output data width not evenly divisble");
117+
$error("Error: output data width not evenly divisble (instance %m)");
118118
$finish;
119119
end
120120

121121
if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
122-
$error("Error: word size mismatch");
122+
$error("Error: word size mismatch (instance %m)");
123123
$finish;
124124
end
125125
end

‎rtl/axis_async_fifo.v

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -120,22 +120,22 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH
120120
// check configuration
121121
initial begin
122122
if (FRAME_FIFO && !LAST_ENABLE) begin
123-
$error("Error: FRAME_FIFO set requires LAST_ENABLE set");
123+
$error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
124124
$finish;
125125
end
126126

127127
if (DROP_BAD_FRAME && !FRAME_FIFO) begin
128-
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set");
128+
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)");
129129
$finish;
130130
end
131131

132132
if (DROP_WHEN_FULL && !FRAME_FIFO) begin
133-
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set");
133+
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)");
134134
$finish;
135135
end
136136

137137
if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
138-
$error("Error: Invalid USER_BAD_FRAME_MASK value");
138+
$error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
139139
$finish;
140140
end
141141
end

‎rtl/axis_async_fifo_adapter.v

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -133,17 +133,17 @@ parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT;
133133
// bus width assertions
134134
initial begin
135135
if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
136-
$error("Error: input data width not evenly divisble");
136+
$error("Error: input data width not evenly divisble (instance %m)");
137137
$finish;
138138
end
139139

140140
if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
141-
$error("Error: output data width not evenly divisble");
141+
$error("Error: output data width not evenly divisble (instance %m)");
142142
$finish;
143143
end
144144

145145
if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
146-
$error("Error: word size mismatch");
146+
$error("Error: word size mismatch (instance %m)");
147147
$finish;
148148
end
149149
end

‎rtl/axis_fifo.v

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -113,22 +113,22 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH
113113
// check configuration
114114
initial begin
115115
if (FRAME_FIFO && !LAST_ENABLE) begin
116-
$error("Error: FRAME_FIFO set requires LAST_ENABLE set");
116+
$error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
117117
$finish;
118118
end
119119

120120
if (DROP_BAD_FRAME && !FRAME_FIFO) begin
121-
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set");
121+
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)");
122122
$finish;
123123
end
124124

125125
if (DROP_WHEN_FULL && !FRAME_FIFO) begin
126-
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set");
126+
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)");
127127
$finish;
128128
end
129129

130130
if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
131-
$error("Error: Invalid USER_BAD_FRAME_MASK value");
131+
$error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
132132
$finish;
133133
end
134134
end

‎rtl/axis_fifo_adapter.v

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -129,17 +129,17 @@ parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT;
129129
// bus width assertions
130130
initial begin
131131
if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
132-
$error("Error: input data width not evenly divisble");
132+
$error("Error: input data width not evenly divisble (instance %m)");
133133
$finish;
134134
end
135135

136136
if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
137-
$error("Error: output data width not evenly divisble");
137+
$error("Error: output data width not evenly divisble (instance %m)");
138138
$finish;
139139
end
140140

141141
if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
142-
$error("Error: word size mismatch");
142+
$error("Error: word size mismatch (instance %m)");
143143
$finish;
144144
end
145145
end

‎rtl/axis_frame_length_adjust.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@ localparam DATA_WORD_WIDTH = DATA_WIDTH / KEEP_WIDTH;
102102
// bus width assertions
103103
initial begin
104104
if (DATA_WORD_WIDTH * KEEP_WIDTH != DATA_WIDTH) begin
105-
$error("Error: data width not evenly divisble");
105+
$error("Error: data width not evenly divisble (instance %m)");
106106
$finish;
107107
end
108108
end

‎rtl/axis_switch.v

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,7 @@ integer i, j;
113113
// check configuration
114114
initial begin
115115
if (DEST_WIDTH < CL_M_COUNT) begin
116-
$error("Error: DEST_WIDTH too small for port count");
116+
$error("Error: DEST_WIDTH too small for port count (instance %m)");
117117
$finish;
118118
end
119119

@@ -126,15 +126,15 @@ initial begin
126126
if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] == M_BASE[j*DEST_WIDTH +: DEST_WIDTH]) begin
127127
$display("%d: %08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH]);
128128
$display("%d: %08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH]);
129-
$error("Error: ranges overlap");
129+
$error("Error: ranges overlap (instance %m)");
130130
$finish;
131131
end
132132
end
133133
end
134134
end else begin
135135
for (i = 0; i < M_COUNT; i = i + 1) begin
136136
if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] > M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin
137-
$error("Error: invalid range");
137+
$error("Error: invalid range (instance %m)");
138138
$finish;
139139
end
140140
end
@@ -144,7 +144,7 @@ initial begin
144144
if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[j*DEST_WIDTH +: DEST_WIDTH] && M_BASE[j*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin
145145
$display("%d: %08x-%08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH]);
146146
$display("%d: %08x-%08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH], M_TOP[j*DEST_WIDTH +: DEST_WIDTH]);
147-
$error("Error: ranges overlap");
147+
$error("Error: ranges overlap (instance %m)");
148148
$finish;
149149
end
150150
end

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