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Testbench updates
1 parent b60886a commit e0f7404

36 files changed

+205
-165
lines changed

tb/test_axis_adapter_64_8.py

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -157,12 +157,14 @@ def wait_normal():
157157

158158
def wait_pause_source():
159159
while s_axis_tvalid or m_axis_tvalid:
160-
source_pause.next = True
161-
yield clk.posedge
162160
yield clk.posedge
163161
yield clk.posedge
164162
source_pause.next = False
165163
yield clk.posedge
164+
source_pause.next = True
165+
yield clk.posedge
166+
167+
source_pause.next = False
166168

167169
def wait_pause_sink():
168170
while s_axis_tvalid or m_axis_tvalid:

tb/test_axis_adapter_8_64.py

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -157,12 +157,14 @@ def wait_normal():
157157

158158
def wait_pause_source():
159159
while s_axis_tvalid or m_axis_tvalid:
160-
source_pause.next = True
161-
yield clk.posedge
162160
yield clk.posedge
163161
yield clk.posedge
164162
source_pause.next = False
165163
yield clk.posedge
164+
source_pause.next = True
165+
yield clk.posedge
166+
167+
source_pause.next = False
166168

167169
def wait_pause_sink():
168170
while s_axis_tvalid or m_axis_tvalid:

tb/test_axis_arb_mux_4.py

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ def check():
302302
yield delay(100)
303303

304304
yield clk.posedge
305-
print("test 5: alterate pause source")
305+
print("test 5: alternate pause source")
306306
current_test.next = 5
307307

308308
test_frame1 = axis_ep.AXIStreamFrame(
@@ -327,14 +327,17 @@ def check():
327327
yield clk.posedge
328328

329329
while s_axis_tvalid:
330-
for k in range(S_COUNT):
331-
source_pause_list[k].next = True
332-
yield clk.posedge
333330
yield clk.posedge
334331
yield clk.posedge
335332
for k in range(S_COUNT):
336333
source_pause_list[k].next = False
337334
yield clk.posedge
335+
for k in range(S_COUNT):
336+
source_pause_list[k].next = True
337+
yield clk.posedge
338+
339+
for k in range(S_COUNT):
340+
source_pause_list[k].next = False
338341

339342
yield sink.wait()
340343
rx_frame = sink.recv()
@@ -349,7 +352,7 @@ def check():
349352
yield delay(100)
350353

351354
yield clk.posedge
352-
print("test 6: alterate pause sink")
355+
print("test 6: alternate pause sink")
353356
current_test.next = 6
354357

355358
test_frame1 = axis_ep.AXIStreamFrame(

tb/test_axis_arb_mux_4_64.py

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ def check():
302302
yield delay(100)
303303

304304
yield clk.posedge
305-
print("test 5: alterate pause source")
305+
print("test 5: alternate pause source")
306306
current_test.next = 5
307307

308308
test_frame1 = axis_ep.AXIStreamFrame(
@@ -327,14 +327,17 @@ def check():
327327
yield clk.posedge
328328

329329
while s_axis_tvalid:
330-
for k in range(S_COUNT):
331-
source_pause_list[k].next = True
332-
yield clk.posedge
333330
yield clk.posedge
334331
yield clk.posedge
335332
for k in range(S_COUNT):
336333
source_pause_list[k].next = False
337334
yield clk.posedge
335+
for k in range(S_COUNT):
336+
source_pause_list[k].next = True
337+
yield clk.posedge
338+
339+
for k in range(S_COUNT):
340+
source_pause_list[k].next = False
338341

339342
yield sink.wait()
340343
rx_frame = sink.recv()
@@ -349,7 +352,7 @@ def check():
349352
yield delay(100)
350353

351354
yield clk.posedge
352-
print("test 6: alterate pause sink")
355+
print("test 6: alternate pause sink")
353356
current_test.next = 6
354357

355358
test_frame1 = axis_ep.AXIStreamFrame(

tb/test_axis_async_fifo.py

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -320,12 +320,14 @@ def check():
320320
yield s_clk.posedge
321321

322322
while s_axis_tvalid or m_axis_tvalid:
323-
source_pause.next = True
324-
yield s_clk.posedge
325323
yield s_clk.posedge
326324
yield s_clk.posedge
327325
source_pause.next = False
328326
yield s_clk.posedge
327+
source_pause.next = True
328+
yield s_clk.posedge
329+
330+
source_pause.next = False
329331

330332
yield sink.wait()
331333
rx_frame = sink.recv()

tb/test_axis_async_fifo_64.py

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -320,12 +320,14 @@ def check():
320320
yield s_clk.posedge
321321

322322
while s_axis_tvalid or m_axis_tvalid:
323-
source_pause.next = True
324-
yield s_clk.posedge
325323
yield s_clk.posedge
326324
yield s_clk.posedge
327325
source_pause.next = False
328326
yield s_clk.posedge
327+
source_pause.next = True
328+
yield s_clk.posedge
329+
330+
source_pause.next = False
329331

330332
yield sink.wait()
331333
rx_frame = sink.recv()

tb/test_axis_async_frame_fifo.py

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -418,12 +418,14 @@ def check():
418418
yield s_clk.posedge
419419

420420
while s_axis_tvalid or m_axis_tvalid:
421-
source_pause.next = True
422-
yield s_clk.posedge
423421
yield s_clk.posedge
424422
yield s_clk.posedge
425423
source_pause.next = False
426424
yield s_clk.posedge
425+
source_pause.next = True
426+
yield s_clk.posedge
427+
428+
source_pause.next = False
427429

428430
yield sink.wait()
429431
rx_frame = sink.recv()

tb/test_axis_async_frame_fifo_64.py

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -418,12 +418,14 @@ def check():
418418
yield s_clk.posedge
419419

420420
while s_axis_tvalid or m_axis_tvalid:
421-
source_pause.next = True
422-
yield s_clk.posedge
423421
yield s_clk.posedge
424422
yield s_clk.posedge
425423
source_pause.next = False
426424
yield s_clk.posedge
425+
source_pause.next = True
426+
yield s_clk.posedge
427+
428+
source_pause.next = False
427429

428430
yield sink.wait()
429431
rx_frame = sink.recv()

tb/test_axis_broadcast_4.py

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -252,16 +252,12 @@ def check():
252252

253253
yield delay(64)
254254
yield clk.posedge
255-
sink_pause_list[0].next = True
256-
sink_pause_list[1].next = True
257-
sink_pause_list[2].next = True
258-
sink_pause_list[3].next = True
255+
for k in range(M_COUNT):
256+
sink_pause_list[k].next = True
259257
yield delay(32)
260258
yield clk.posedge
261-
sink_pause_list[0].next = False
262-
sink_pause_list[1].next = False
263-
sink_pause_list[2].next = False
264-
sink_pause_list[3].next = False
259+
for k in range(M_COUNT):
260+
sink_pause_list[k].next = False
265261

266262
for sink in sink_list:
267263
yield sink.wait()
@@ -382,17 +378,13 @@ def check():
382378
yield clk.posedge
383379

384380
while s_axis_tvalid or m_axis_tvalid:
385-
sink_pause_list[0].next = True
386-
sink_pause_list[1].next = True
387-
sink_pause_list[2].next = True
388-
sink_pause_list[3].next = True
381+
for k in range(M_COUNT):
382+
sink_pause_list[k].next = True
389383
yield clk.posedge
390384
yield clk.posedge
391385
yield clk.posedge
392-
sink_pause_list[0].next = False
393-
sink_pause_list[1].next = False
394-
sink_pause_list[2].next = False
395-
sink_pause_list[3].next = False
386+
for k in range(M_COUNT):
387+
sink_pause_list[k].next = False
396388
yield clk.posedge
397389

398390
for sink in sink_list:

tb/test_axis_cobs_decode.py

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,6 @@ def cobs_decode(block):
7777
block = bytearray(block)
7878
dec = bytearray()
7979

80-
it = iter(bytearray(block))
8180
code = 0
8281

8382
i = 0
@@ -202,12 +201,14 @@ def wait_pause_source():
202201
i = max(0, i-1)
203202
if s_axis_tvalid or m_axis_tvalid or not source.empty():
204203
i = 2
205-
source_pause.next = True
206-
yield clk.posedge
207204
yield clk.posedge
208205
yield clk.posedge
209206
source_pause.next = False
210207
yield clk.posedge
208+
source_pause.next = True
209+
yield clk.posedge
210+
211+
source_pause.next = False
211212

212213
def wait_pause_sink():
213214
i = 2

tb/test_axis_cobs_encode.py

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,6 @@ def cobs_decode(block):
7878
block = bytearray(block)
7979
dec = bytearray()
8080

81-
it = iter(bytearray(block))
8281
code = 0
8382

8483
i = 0
@@ -203,12 +202,14 @@ def wait_pause_source():
203202
i = max(0, i-1)
204203
if s_axis_tvalid or m_axis_tvalid or not source.empty():
205204
i = 2
206-
source_pause.next = True
207-
yield clk.posedge
208205
yield clk.posedge
209206
yield clk.posedge
210207
source_pause.next = False
211208
yield clk.posedge
209+
source_pause.next = True
210+
yield clk.posedge
211+
212+
source_pause.next = False
212213

213214
def wait_pause_sink():
214215
i = 2

tb/test_axis_cobs_encode_zero_frame.py

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,6 @@ def cobs_decode(block):
7878
block = bytearray(block)
7979
dec = bytearray()
8080

81-
it = iter(bytearray(block))
8281
code = 0
8382

8483
i = 0
@@ -204,12 +203,14 @@ def wait_pause_source():
204203
i = max(0, i-1)
205204
if s_axis_tvalid or m_axis_tvalid or not source.empty():
206205
i = 2
207-
source_pause.next = True
208-
yield clk.posedge
209206
yield clk.posedge
210207
yield clk.posedge
211208
source_pause.next = False
212209
yield clk.posedge
210+
source_pause.next = True
211+
yield clk.posedge
212+
213+
source_pause.next = False
213214

214215
def wait_pause_sink():
215216
i = 2

tb/test_axis_demux_4.py

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -322,7 +322,7 @@ def check():
322322
yield delay(100)
323323

324324
yield clk.posedge
325-
print("test 5: alterate pause source")
325+
print("test 5: alternate pause source")
326326
current_test.next = 5
327327

328328
select.next = 1
@@ -349,13 +349,15 @@ def check():
349349
yield clk.posedge
350350

351351
while s_axis_tvalid:
352-
source_pause.next = True
353-
yield clk.posedge
354352
yield clk.posedge
353+
select.next = 2
355354
yield clk.posedge
356355
source_pause.next = False
357356
yield clk.posedge
358-
select.next = 2
357+
source_pause.next = True
358+
yield clk.posedge
359+
360+
source_pause.next = False
359361

360362
yield sink_list[1].wait()
361363
rx_frame = sink_list[1].recv()
@@ -370,7 +372,7 @@ def check():
370372
yield delay(100)
371373

372374
yield clk.posedge
373-
print("test 6: alterate pause sink")
375+
print("test 6: alternate pause sink")
374376
current_test.next = 6
375377

376378
select.next = 1
@@ -397,17 +399,13 @@ def check():
397399
yield clk.posedge
398400

399401
while s_axis_tvalid:
400-
sink_pause_list[0].next = True
401-
sink_pause_list[1].next = True
402-
sink_pause_list[2].next = True
403-
sink_pause_list[3].next = True
402+
for k in range(M_COUNT):
403+
sink_pause_list[k].next = True
404404
yield clk.posedge
405405
yield clk.posedge
406406
yield clk.posedge
407-
sink_pause_list[0].next = False
408-
sink_pause_list[1].next = False
409-
sink_pause_list[2].next = False
410-
sink_pause_list[3].next = False
407+
for k in range(M_COUNT):
408+
sink_pause_list[k].next = False
411409
yield clk.posedge
412410
select.next = 2
413411

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