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Account for merged registers
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syn/axis_async_fifo.tcl

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -38,11 +38,15 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == axis_async_fifo ||
3838
set_property ASYNC_REG TRUE $reset_ffs
3939
set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}]
4040

41-
set_false_path -to [get_pins $fifo_inst/s_rst_sync2_reg_reg/D]
42-
set_max_delay -from [get_cells $fifo_inst/s_rst_sync2_reg_reg] -to [get_cells $fifo_inst/s_rst_sync3_reg_reg] $min_clk_period
41+
if {[llength [get_cells $fifo_inst/s_rst_sync2_reg_reg]]} {
42+
set_false_path -to [get_pins $fifo_inst/s_rst_sync2_reg_reg/D]
43+
set_max_delay -from [get_cells $fifo_inst/s_rst_sync2_reg_reg] -to [get_cells $fifo_inst/s_rst_sync3_reg_reg] $min_clk_period
44+
}
4345

44-
set_false_path -to [get_pins $fifo_inst/m_rst_sync2_reg_reg/D]
45-
set_max_delay -from [get_cells $fifo_inst/m_rst_sync2_reg_reg] -to [get_cells $fifo_inst/m_rst_sync3_reg_reg] $min_clk_period
46+
if {[llength [get_cells $fifo_inst/m_rst_sync2_reg_reg]]} {
47+
set_false_path -to [get_pins $fifo_inst/m_rst_sync2_reg_reg/D]
48+
set_max_delay -from [get_cells $fifo_inst/m_rst_sync2_reg_reg] -to [get_cells $fifo_inst/m_rst_sync3_reg_reg] $min_clk_period
49+
}
4650

4751
# pointer synchronization
4852
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/(wr|rd)_ptr_gray_sync\[12\]_reg_reg\\\[\\d+\\\]" -filter "PARENT == $fifo_inst"]

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