raid: R-V V pq_gen xor_gen

Release_notes.txt

@@ -1,4 +1,4 @@
-v2.31.1 Intel Intelligent Storage Acceleration Library Release Notes
+v2.32 Intel Intelligent Storage Acceleration Library Release Notes
 ====================================================================
 
 RELEASE NOTE CONTENTS
@@ -139,6 +139,17 @@ v2.10
 3. CHANGE LOG & FEATURES ADDED
 ------------------------------
 
+v2.32
+
+* RISCV support.
+  - Initial riscv64 support with runtime and build-time CPU feature detection.
+
+* Igzip compression improvements:
+  - Added new RVV adler32 implementations.
+
+* RAID improvements:
+  - Added new RVV xor_gen, pq_gen implementations.
+
 v2.31
 
 * API changes:

igzip/riscv64/Makefile.am

@@ -10,7 +10,7 @@
 #      notice, this list of conditions and the following disclaimer in
 #      the documentation and/or other materials provided with the
 #      distribution.
-#    * Neither the name of ISCAS Corporation nor the names of its
+#    * Neither the name of ISCAS nor the names of its
 #      contributors may be used to endorse or promote products derived
 #      from this software without specific prior written permission.
 #

igzip/riscv64/igzip_isal_adler32_rvv.S

@@ -10,7 +10,7 @@
       notice, this list of conditions and the following disclaimer in
       the documentation and/or other materials provided with the
       distribution.
-    * Neither the name of ISCAS Corporation nor the names of its
+    * Neither the name of ISCAS nor the names of its
       contributors may be used to endorse or promote products derived
       from this software without specific prior written permission.
 

igzip/riscv64/igzip_multibinary_riscv64.S

@@ -10,7 +10,7 @@
       notice, this list of conditions and the following disclaimer in
       the documentation and/or other materials provided with the
       distribution.
-    * Neither the name of ISCAS Corporation nor the names of its
+    * Neither the name of ISCAS nor the names of its
       contributors may be used to endorse or promote products derived
       from this software without specific prior written permission.
 

igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c

@@ -10,7 +10,7 @@
       notice, this list of conditions and the following disclaimer in
       the documentation and/or other materials provided with the
       distribution.
-    * Neither the name of ISCAS Corporation nor the names of its
+    * Neither the name of ISCAS nor the names of its
       contributors may be used to endorse or promote products derived
       from this software without specific prior written permission.
 

include/riscv64_multibinary.h

@@ -10,7 +10,7 @@
       notice, this list of conditions and the following disclaimer in
       the documentation and/or other materials provided with the
       distribution.
-    * Neither the name of ISCAS Corporation nor the names of its
+    * Neither the name of ISCAS nor the names of its
       contributors may be used to endorse or promote products derived
       from this software without specific prior written permission.
 

raid/Makefile.am

@@ -29,11 +29,12 @@
 
 include raid/aarch64/Makefile.am
 
+include raid/riscv64/Makefile.am
+
 lsrc        += 	raid/raid_base.c
 
 lsrc_base_aliases += raid/raid_base_aliases.c
 lsrc_ppc64le      += raid/raid_base_aliases.c
-lsrc_riscv64      += raid/raid_base_aliases.c
 
 lsrc_x86_64 += \
 		raid/xor_gen_sse.asm \

raid/raid_base.c

@@ -138,7 +138,5 @@ xor_check_base(int vects, int len, void **array)
                         break;
                 }
         }
-        if (fail && len > 0)
-                return len;
         return fail;
 }

raid/riscv64/Makefile.am

@@ -0,0 +1,34 @@
+########################################################################
+#  Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#    * Redistributions of source code must retain the above copyright
+#      notice, this list of conditions and the following disclaimer.
+#    * Redistributions in binary form must reproduce the above copyright
+#      notice, this list of conditions and the following disclaimer in
+#      the documentation and/or other materials provided with the
+#      distribution.
+#    * Neither the name of ISCAS nor the names of its
+#      contributors may be used to endorse or promote products derived
+#      from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+########################################################################
+
+lsrc_riscv64 += \
+	raid/riscv64/raid_multibinary_riscv64_dispatcher.c \
+	raid/riscv64/raid_multibinary_riscv64.S \
+	raid/riscv64/raid_pq_gen_rvv.S \
+	raid/riscv64/raid_xor_gen_rvv.S

raid/riscv64/raid_multibinary_riscv64.S

@@ -0,0 +1,41 @@
+/**********************************************************************
+  Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of ISCAS nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************/
+
+#include "riscv64_multibinary.h"
+
+#if HAVE_RVV
+    mbin_interface		pq_gen
+    mbin_interface		xor_gen
+#else
+    mbin_interface_base         pq_gen pq_gen_base
+    mbin_interface_base         xor_gen xor_gen_base
+#endif
+
+mbin_interface_base pq_check pq_check_base
+mbin_interface_base xor_check xor_check_base

raid/riscv64/raid_multibinary_riscv64_dispatcher.c

@@ -0,0 +1,60 @@
+/**********************************************************************
+  Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of ISCAS nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************/
+#include "riscv64_multibinary.h"
+
+extern int
+pq_gen_rvv(int vects, int len, void **array);
+extern int
+pq_gen_base(int vects, int len, void **array);
+extern int
+xor_gen_rvv(int vects, int len, void **array);
+extern int
+xor_gen_base(int vects, int len, void **array);
+
+DEFINE_INTERFACE_DISPATCHER(pq_gen)
+{
+#if HAVE_RVV
+        const unsigned long hwcap = getauxval(AT_HWCAP);
+        if (hwcap & HWCAP_RV('V'))
+                return pq_gen_rvv;
+        else
+#endif
+                return pq_gen_base;
+}
+
+DEFINE_INTERFACE_DISPATCHER(xor_gen)
+{
+#if HAVE_RVV
+        const unsigned long hwcap = getauxval(AT_HWCAP);
+        if (hwcap & HWCAP_RV('V'))
+                return xor_gen_rvv;
+        else
+#endif
+                return xor_gen_base;
+}

raid/riscv64/raid_pq_gen_rvv.S

@@ -0,0 +1,105 @@
+/**********************************************************************
+  Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in
+      the documentation and/or other materials provided with the
+      distribution.
+    * Neither the name of ISCAS nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************/
+#if HAVE_RVV
+.option         arch, +v
+.global         pq_gen_rvv
+.type           pq_gen_rvv, %function
+pq_gen_rvv:
+    srli        a1, a1, 3                  // blocks = len / 8
+    beqz        a1, ret0                   // blocks <= 0
+    addi        a6, a0, -3                 // j = vects - 4
+    blez        a6, ret1                   // vects < 4
+
+    slli        t0, a0, 3                  // t0 = vects * 8
+    add         t0, a2, t0                 // array + vects * 8
+    li          t1, 0x8080808080808080     // bit7
+    li          t2, 0xfefefefefefefefe     // notbit0
+    li          t3, 0x1d1d1d1d1d1d1d1d     // gf8poly
+    ld          a3, -24(t0)                // src[vects-3]
+    ld          a4, -16(t0)                // p
+    ld          a5, -8(t0)                 // q
+    mv          t6, a1                     // save blocks
+    mv          t5, a4                     // save p
+    mv          a7, a5                     // save q
+
+init_pq:
+    vsetvli     t4, t6, e64, m4, ta, ma
+    vle64.v     v0, (a3)
+    vse64.v     v0, (a4)                   // init p
+    vse64.v     v0, (a5)                   // init q
+    sub         t6, t6, t4
+    slli        t4, t4, 3
+    add         a3, a3, t4
+    add         a4, a4, t4
+    add         a5, a5, t4
+    bnez        t6, init_pq
+
+outer_j:
+    mv          a4, t5                     // restore p
+    mv          a5, a7                     // restore q
+    mv          t6, a1                     // restore blocks
+    ld          a0, -32(t0)                // src[j]
+
+inner_block:
+    vsetvli     t4, t6, e64, m4, ta, ma
+    vle64.v     v8, (a0)                   // s
+    vle64.v     v0, (a4)                   // p
+    vle64.v     v4, (a5)                   // q
+    vxor.vv     v0, v0, v8                 // p ^= s
+    vand.vx     v20, v4, t1                // q & bit7
+    vsll.vi     v24, v4, 1                 // (q << 1)
+    vand.vx     v24, v24, t2               // (q << 1) & notbit0
+    vsrl.vi     v16, v20, 7                // (q & bit7)>>7
+    vsll.vi     v20, v20, 1                // (q & bit7)<<1
+    vsub.vv     v20, v20, v16              // (q & bit7)<<1 - (q & bit7)>>7
+    vand.vx     v20, v20, t3               // ((q & bit7)<<1 - (q & bit7)>>7) & gf8poly
+    vxor.vv     v4, v24, v20               // ((q << 1) & notbit0) ^
+    vxor.vv     v4, v4, v8                 // s^
+    vse64.v     v0, (a4)                   // p
+    vse64.v     v4, (a5)                   // q
+    sub         t6, t6, t4                 // blocks
+    slli        t4, t4, 3
+    add         a4, a4, t4                 // p+=
+    add         a5, a5, t4                 // q+=
+    add         a0, a0, t4                 // s+=
+    bnez        t6, inner_block
+
+    addi        a6, a6, -1
+    addi        t0, t0, -8
+    bnez        a6, outer_j
+
+ret0:
+    li a0, 0
+    ret
+
+ret1:
+    li a0, 1
+    ret
+
+#endif