axi-bus

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Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus

Example workflow project for VHDL development.

workflow vhdl tcl vivado axi axi-bus tcl-scripts cocotb cocotb-testing

Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.

vhdl performance-analysis axi-bus axi-stream axi4 latency-analysis

5-stage-Pipeline-CPU with AXI bus

systemverilog vlsi system-design axi-bus vlsi-design

This is a hardware project of an inline memory compressor that reduces the amount of memory used by embedded systems

arm fpga hardware vhdl tcl verilog compressor axi-bus zynq-7000

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