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Ready to Learn,Unlearn and Relearn
✍️
Ready to Learn,Unlearn and Relearn
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Sibakumarpanda/README.md

Hi , Welcome to my Github. I'm Siba Kumar Panda 👋

  • 🔭 I’m currently working on VLSI Design & Verification domain
  • 🌱 I’m currently learning lots of stuff related to advanced verification
  • 👯 I’m looking to collaborate on research in VLSI computing , VLSI architecture ,VLSI verification
  • 🤔 Enjoy in coding with : Verilog , SV , UVM
  • 💬 Goal : Learn & contribute more to open source projects
  • 📫 How to reach me: Just drop me an email
  • 😄 Pronouns: He/Him
  • ⚡ Fun fact: Love to Learn , Unlearn & UnLearn

Pinned Loading

  1. SystemVerilog_Constraint_Coding_by_Siba Public

    SystemVerilog Constraints Practice

    SystemVerilog 1

  2. Systemverilog_Coding_Practice_by_Siba Public

    Aim to explore the System Verilog concepts with Hands on , which could be used for verification

    SystemVerilog 2

  3. Sibakumarpanda Public

    Config files for my GitHub profile

    1

  4. UVM_Concepts Public

    Includes advance concepts of verification

    1

  5. AXI_verification_with_UVM Public

    AXI Verif IP development

    1

  6. Systemverilog_UVM_coding_TB_develop_guideline_Siba Public

    It focuses on general/universal coding styles as well as guideline for creating files/directories in SV,UVM

    1