Registers: FF04
Clock division and distribution. Reset signal buffering and distribution.
Registers: FF0F
Joypad interrupt generation. Interrupt registering and acknowledgement.
Registers: FF05, FF06, FF07
Clock selection, timer counter and comparator. Timer interrupt generation.
Registers: FF46
Address counter, access sequencer.
Registers: FF00
External I/O, special handling for test modes.
Registers: FF01, FF02
Bit counter, shift register, serial interrupt generation.
Registers: FF50, FF60
Boot ROM address decoding, lockout, HRAM decoding, test register.
Address and data bus direction control, multiplexing and buffering.
Registers: FF24, FF25, FF26
Audio section clock generation, reset distribution.
Decoding for all the audio-related registers. Analog section power control.
Registers: FF10, FF11, FF12, FF13, FF14
Sound channel 1 registers read/write.
Registers: FF13, FF14
Sound channel 1 frequency sweep logic.
Sound channel 1 main logic: Length timer, EG timer, EG, sweep timer, sweep shift counter, waveform duty selection.
Registers: FF16, FF17, FF18, FF19
Sound channel 2 registers read/write.
Sound channel 2 main logic: Length timer, EG timer, EG, waveform duty selection.
Registers: FF1A, FF1B, FF1C, FF1D, FF1E
Sound channel 3 registers read/write.
CPU and APU read access control for Wave RAM, byte splitter.
Sound channel 3 main logic: Length timer, attenuator, wave RAM address generator.
Registers: FF20, FF21, FF22, FF23
Sound channel 4 registers read/write.
Sound channel 4 main logic: Length timer, EG timer, EG, frequency selection, LFSR.
Registers: FF41
Video sequencing, interrupt generation, X and Y counters, raster number comparator.
Decoding for all the video-related registers.
Registers: FF40, FF42, FF43, FF44, FF45, FF4A, FF4B
Video registers read/write.
Signal generation for the LCD. Horizontal and vertical sync along with others.
Address and data bus direction control, multiplexing, buffering and control signal generation for external VRAM.
Background layer tile map address generation, shifter for the BG-to-sprite priority bit.
Window layer tile map address generation, window and background rendering logic, X and Y comparators.
Sequencing and arbitrating, parsing counter, address multiplexing, control signal generation.
Raster comparator for sprite parsing, X priority, more sequencing logic, triggers for sprite store.
Ten 10-bit registers storing Y-matched sprite numbers (6 bits) and rendering raster indexes (4 bits).
Ten X comparators used to detect when to start rendering sprites.
Background pixel data loader and shifters.
Sprite pixel data loader and shifters.
Sprite palette loader and shifter, pixel opacity detection.
Pixel data multiplexing between background, sprite palette 0 and sprite palette 1 for final output.
Registers: FF47, FF48, FF49
Palette registers read/write.