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Pull requests: llvm/circt
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[Support] Add relative path caching to InstancePathCache
#8489
opened May 17, 2025 by
uenoku
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[SharedResourcesProblem] [Simplex Scheduler] Simplex scheduler deals with multiple resource constraints
#8480
opened May 13, 2025 by
jiahanxie353
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[SCFToCalyx] Modify top-level function in place and propagate external memory allocations
#8446
opened Apr 25, 2025 by
jiahanxie353
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[PyRTG] Refactor targets/configs
RTG
Involving the `rtg` dialect
#8399
opened Apr 7, 2025 by
maerhart
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[RTG] Add MemoryAllocation pass to pipeline
RTG
Involving the `rtg` dialect
#8397
opened Apr 6, 2025 by
maerhart
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[RTG] Add MemoryAllocation pass
RTG
Involving the `rtg` dialect
#8395
opened Apr 6, 2025 by
maerhart
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[ImportVerilog] Convert the unpacked array to a simple bit vector
#8392
opened Apr 4, 2025 by
AnnuCode
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[RTG][Elaboration] Improve how tests are matched with targets
RTG
Involving the `rtg` dialect
#8391
opened Apr 4, 2025 by
maerhart
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[RTG][Elaboration] Treat randomized sequences as regular identity values
RTG
Involving the `rtg` dialect
#8389
opened Apr 3, 2025 by
maerhart
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[RTG][Elaboration] Properly handle values with identity
RTG
Involving the `rtg` dialect
#8388
opened Apr 3, 2025 by
maerhart
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When replacing a register with its reset value, attempt width coercion
FIRRTL
Involving the `firrtl` dialect
#8379
opened Apr 1, 2025 by
rwy7
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Add a few mux-of-const and reg-of-and/or canonicalizers.
FIRRTL
Involving the `firrtl` dialect
#8307
opened Mar 7, 2025 by
rwy7
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[circt-verilog-lsp] Add inlay hints support for Verilog LSP server
#8303
opened Mar 6, 2025 by
uenoku
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[circt-verilog-lsp][vscode] Add initial VS Code extension configuration for CIRCT Verilog LSP
#8281
opened Feb 27, 2025 by
uenoku
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[circt-verilog-lsp] Add definition and reference providers
#8280
opened Feb 27, 2025 by
uenoku
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[ImportVerilog] add unpacked array concatenation
Moore
#8270
opened Feb 24, 2025 by
chenbo-again
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[circt-synth] Implemented AIG node balancing algorithm
#8262
opened Feb 21, 2025 by
Max-astro
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[ImportVerilog]Support the delay control.
ImportVerilog
Moore
#8259
opened Feb 20, 2025 by
terapines-osc-1
•
Draft
[MooreToCore]Remove unexpected observed values for WaitOp.
bug
Something isn't working
Moore
#8255
opened Feb 19, 2025 by
terapines-osc-1
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