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For loops in Nmigen

Status: Open.

#350 In m-labs/nmigen;

· ParasVekariya opened on Sep 4, 2022

No clk being generated

Status: Open.

#349 In m-labs/nmigen;

· mayank-kabra2001 opened on Dec 30, 2021

Want to know some details of the back

Status: Open.

#346 In m-labs/nmigen;

· ekikun opened on May 27, 2021

Improve readability of assignments and add contexts for clock domains

Status: Open.

#345 In m-labs/nmigen;

· ildus opened on Apr 5, 2021

Signal decoder inference for Enums doesn't work for Layout members

Status: Open.

#333 In m-labs/nmigen;

· shawnanastasio opened on May 26, 2020

lambdasoc analysis & synthesis got error on intel platform.

Status: Open.

#331 In m-labs/nmigen;

· franz-git opened on May 21, 2020

Generating async negedge reset

Status: Open.

#329 In m-labs/nmigen;

· tariqafzal opened on May 15, 2020

Hierarchical Redundancy in emitted Verilog

Status: Open.

#328 In m-labs/nmigen;

· BracketMaster opened on May 6, 2020

Installation fails if wheel not installed

Status: Open.

#323 In m-labs/nmigen;

· alanvgreen opened on Apr 3, 2020

hdl.ast.Value.word_select() works incorrectly on actual platform (ECP5 Versa)

bug

Status: Open.

#310 In m-labs/nmigen;

· ghost opened on Jan 23, 2020

Support Platforms that include an existing design and expose interface to that design as Resource

feature

Status: Open.

#308 In m-labs/nmigen;

· smunaut opened on Jan 19, 2020

Add EnableSignal, useful for making Instances compatible with EnableInserter

feature

Status: Open.

#285 In m-labs/nmigen;

· Fatsie opened on Dec 25, 2019

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