The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

CoreIR Symbolic Analyzer

This repo is created to include illustrative examples on object oriented design pattern in SV

The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.

Welcome to the ultimate list of resources for formal verification techniques and tools. This repository aims to provide an organized collection of high-quality resources to help professionals, researchers, and enthusiasts stay updated and advance their knowledge in the field.

VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.

Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators

A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.

Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification

A Coq framework to support structural design and proof of hardware cache-coherence protocols

Btor2 parser, circuit mitter, and code optimizer

This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.

Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.

Generate, Simulate & Summarize Verilog Code with GenAI and Iverilog tool

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Specman/e-language syntax for Sublime Text 3

Through a verification environment, this repository uses UVM to handle with multiple clock domains and virtual sequences.

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

Algorithmic C Datatypes