Add tileable RR Graph #3134

amin1377 · 2025-06-11T18:14:24Z

Merging OpenFPGA branch into master branch. PR #2135 explains features of OpenFPGA.

…le info

…rilog-to-routing into add_tileable_rr_graph

amin1377 · 2025-06-30T19:15:22Z

Thanks @vaughnbetz, @soheilshahrouz, and @AlexandreSinger for your reviews. I’ve addressed your comments, and I believe the PR is now ready for the next round of review if you’d like.

…meters since it relies on that value

…rilog-to-routing into add_tileable_rr_graph

vpr/src/route/rr_graph_generation/rr_graph.h

vpr/src/route/rr_graph_generation/rr_graph.cpp

soheilshahrouz · 2025-07-02T18:25:46Z

vpr/src/route/rr_graph_generation/rr_graph.cpp

-                           is_flat,
-                           Warnings,
-                           router_opts.route_verbosity);
+            if (e_graph_type::UNIDIR_TILEABLE != graph_type) {


now that we have two separate rr graph generators, I think we should this function to another file and keep the source code of these two generators as separate as we can

You mean moving create_rr_graph to another?

vpr/src/route/rr_graph_generation/rr_graph.cpp

vpr/src/draw/draw.cpp

vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_graph_builder_utils.cpp

…l.cpp

…ects

…rilog-to-routing into add_tileable_rr_graph

amin1377 · 2025-07-02T23:16:00Z

Thanks @soheilshahrouz. I’ve addressed your comments; please let me know if you have any further suggestions.

soheilshahrouz

These comments apply to most files under tileable_rr_graph/ directory:

integer and bool arguements are passed by const reference. They should be passed by value.
Documentation comments appear at function definition. They should use doxygen style and be moved to the declartion.
Block comments are used for implementation-related comments.
Some range-based loops use const references to iterate over integers (ids). They should iterate by value.

libs/libarchfpga/src/physical_types_util.cpp

libs/libarchfpga/src/vib_inf.h

soheilshahrouz · 2025-07-04T17:53:15Z

libs/libarchfpga/src/vib_inf.h

+/* X_AXIS: Data that describes an x-directed wire segment (CHANX)                     *
+ * Y_AXIS: Data that describes an y-directed wire segment (CHANY)                     *
+ * BOTH_AXIS: Data that can be applied to both x-directed and y-directed wire segment */
+enum class e_parallel_axis {


This enum is used even when VIB is not used. I think it should be move to a different file

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_utils.h

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.h

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp

…rilog-to-routing into add_tileable_rr_graph

amin1377 added 19 commits June 11, 2025 09:55

[vpr][rr_graph] add tileable rr graph dir

b6371d2

[vpr][rr_graph] move tileable rr graph dir uner rr_graph_generation

77781b4

[vpr][route] update rr_graph generation with tileable rr graph

cf95e2c

[vpr][util] add is_inter_cluster_node for vib arch

431923c

[vpr][route] update router lookahead with tileable rr graph

d62fb79

[vpr][blif] use regex to find param val

02a56e9

[vpr][base] update with tileable rr graph

204a794

[vpr][route] remove unused param

7edf56d

[lib][arch] add vib processing

f5e8061

[lib][arch] add vib_inf

14064c7

[libs][rr_graph] update lib rr graph with tileable

49b04b0

[libs][rr graph][io] update read/write rr graph functions with tileab…

c6df91a

…le info

[libs][rr graph][io] update rr_grpah utils with tileable info

bf19150

[lib][rr_graph] add vtr tokenizer

3970db7

[lib][util] update capnp and util with open fpga

797b488

add openfpga doc

cf2dbc8

[vpr][base] add vib grid

0e03dc7

add VIB doc

f8fae78

[vpr][route] fix alloc_and_load_rr_switch_inf definition

5462ccd

github-actions bot added VPR libarchfpga docs lang-cpp libvtrutil labels Jun 11, 2025

amin1377 added 6 commits June 11, 2025 14:15

make format

7cdf5bf

[vtr_flow][test] add openfpga arch

5ad8303

[CI] add openfpga tests

c79ab8f

fix formatting

8eccbcc

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

0cc6f10

…rilog-to-routing into add_tileable_rr_graph

[doc][arch] add tileable doc

5a492c8

amin1377 added 12 commits June 28, 2025 16:00

[libs][arch] fix formatting

205514f

[libs][arch] fix code formatting

28fc161

[libs][arch] replace e_parallel_axis_vib with e_parallel_axis

59f1c86

[libs][rr_graph] fix tileable rr graph code format

55c3f2f

[libs][util] extern out_file_prefix

d168828

[vpr][route] add e_parallel_axis identifier for all members

34d0e65

[libs][arch] add a method to parse tileable arch tags

7beed40

[libs][rr_graph] add comment for tileable rr graph

211c270

make format

4cc25a4

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

b38dbae

…rilog-to-routing into add_tileable_rr_graph

[libs][arch] remove multiple definitons of e_directionality

3e52cd6

[vpr][base] set type name to nullptr if type is null

19452e9

amin1377 added 4 commits June 30, 2025 15:44

[lib][arch] fix clag warning by passing string as c_str

855abff

[libs][arch] set fs value before calling process_tileable_device_para…

ee1c9bd

…meters since it relies on that value

[libs] update submodules

586e56e

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

78c0583

…rilog-to-routing into add_tileable_rr_graph

soheilshahrouz requested changes Jul 2, 2025

View reviewed changes

amin1377 added 5 commits July 2, 2025 18:22

[vpr][util] move find_tile_type_by_name impl under physcial_types_uti…

326077b

…l.cpp

[vpr][route] move alloc_and_load_clb_to_clb_directs under clb2clb_dir…

4c66882

…ects

[vpr][route] fix formatting issues in tileable rr graph

adec8f6

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

5c18569

…rilog-to-routing into add_tileable_rr_graph

make format

abd0116

soheilshahrouz requested changes Jul 4, 2025

View reviewed changes

amin1377 added 5 commits July 7, 2025 20:05

[vpr][tileable] move comments from cpp to .h + fix formatting

e03a84d

[vpr][tileable] fix commenting style

556d499

[vpr][tileable] remove const reference to ids

ec190c3

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

78b4342

…rilog-to-routing into add_tileable_rr_graph

make format

c6d641d

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Add tileable RR Graph #3134

Add tileable RR Graph #3134

amin1377 commented Jun 11, 2025 •

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amin1377 commented Jun 11, 2025 •

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