15 Pull requests merged by 6 people

• Fix Ninja build failure by escaping $(MAKE) in Yosys build command

  #3165 merged Jun 26, 2025

• [AP][Solver] Per-Connection Timing Optimization

  #3155 merged Jun 25, 2025

• Converting Yosys to Submodule

  #3156 merged Jun 25, 2025

• [AP][DP] Added Option to Scale Init T in Annealer

  #3160 merged Jun 24, 2025

• [NetlistWriter] Fixed Tcq SDF Writing for BlackBoxs

  #3142 merged Jun 23, 2025

• [Arch] Added Artix-7-like Devices on the Xilinx 7 Series Capture

  #3139 merged Jun 22, 2025

• Removed twist attribute from RR graph

  #3157 merged Jun 21, 2025

• [Arch] Added Zero ASIC's Z1000 eFPGA Architecture

  #3158 merged Jun 21, 2025

• Congestion-Aware Initial Accumulated Cost

  #3031 merged Jun 20, 2025

• [AP] Marking Global Nets in AP

  #3154 merged Jun 19, 2025

• Fix docs search

  #3150 merged Jun 19, 2025

• Fixed Route Drawing Function

  #3151 merged Jun 19, 2025

• [AP] Generalized Argument Parsing and Added Target Density

  #3148 merged Jun 19, 2025

• [AP][Solver] Ignored Disconnected Blocks in AP Solver

  #3152 merged Jun 19, 2025

• Regenerate nightly test golden results

  #3149 merged Jun 19, 2025

4 Pull requests opened by 3 people

• Flat Routing Visualization

  #3159 opened Jun 22, 2025

• [RouterLookahead] Router Lookahead Report

  #3161 opened Jun 24, 2025

• [Packer] Reorganized Iterative Packer Algorithm

  #3162 opened Jun 24, 2025

• RR Edge ID Verification

  #3164 opened Jun 24, 2025

1 Issue closed by 1 person

• Parsing Errors For Nightly Test 2

  #3145 closed Jun 23, 2025

2 Issues opened by 2 people

• Simultaneous Build Processes

  #3163 opened Jun 24, 2025

• [Libvtrutils] Add Fixed-Point Class

  #3153 opened Jun 19, 2025

7 Unresolved conversations

Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.

• Add tileable RR Graph

  #3134 commented on Jun 25, 2025 • 165 new comments

• Generalize Parmys Mult_Split to Allow for Multipliers Whose Input Widths are not Equal

  #3143 commented on Jun 22, 2025 • 4 new comments

• Allow pin offsets (x, y, layer) in connection block specifications to build the rr-graph

  #2322 commented on Jun 19, 2025 • 0 new comments

• Constant and inverter "replication" during packing

  #2606 commented on Jun 20, 2025 • 0 new comments

• Missing documentaion for some 3D-related tags and fields in the architecture reference

  #2628 commented on Jun 25, 2025 • 0 new comments

• [CI] Added System Verilog Regression Tests to GitHub Runners

  #2885 commented on Jun 24, 2025 • 0 new comments

• Coding Style Guide

  #3026 commented on Jun 25, 2025 • 0 new comments