[Backport v3.7-branch] dts: subsys: npcx: update the required change of npcx9mfb #88695
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The internal flash size of npcx9m7fb is 512KB. Reduce the default Code RAM size from 320KB to 256KB because the Code RAM size is limited by FLASH_SIZE/2 in the Chromebook EC application. Signed-off-by: Tom Chang <CHChang19@nuvoton.com> Signed-off-by: Jun Lin <CHLin56@nuvoton.com> (cherry picked from commit f2e11e4)
There is an issue on the SHI hardware peripheral to detect CS rising/failing with bits CSnFE/CSnRE in the EVSTAT2 register in npcx9m7fb chip. This commit workarounds it by using MIWU to detect the CS rising and failing. Signed-off-by: Tom Chang <CHChang19@nuvoton.com> Signed-off-by: Jun Lin <CHLin56@nuvoton.com> (cherry picked from commit 0726198)
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Backport 0726198~2..0726198 from #78257.
Fixes #88694