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Merged
merged 7 commits into from
May 14, 2025

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dnltz
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@dnltz dnltz commented May 4, 2025

This pull-request adds initial support for ElemRV-N [0], an end-to-end open-source RISC-V microcontroller designed using SpinalHDL successfully tapped-out with IHP's Open PDK [1].

Support for interfaces already exists on my fork and will be added after this PR got merged.

0: https://github.com/aesc-silicon/elemrv
1: https://github.com/IHP-GmbH/IHP-Open-PDK

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the last commit should probably update doc/releases/release-notes-4.2.rst as well

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dnltz commented May 8, 2025

@nordicjm @ycsin @kartben sorry for staling your reviews. I added an uart driver to this pull-request to build and run the hello_world sample.

@dnltz dnltz requested review from nordicjm, ycsin and kartben May 8, 2025 15:47
@dnltz dnltz force-pushed the WIP/dnltz/elemrv-n-board branch 2 times, most recently from e553306 to a62e2ac Compare May 9, 2025 04:16
@dnltz dnltz requested a review from nashif May 9, 2025 04:36
@@ -33,6 +33,7 @@ adh AD Holdings Plc.
adi Analog Devices, Inc.
advantech Advantech Corporation
aeroflexgaisler Aeroflex Gaisler AB
aesc aesc silicon
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All lower-case?

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Changed the name everywhere and capitalized it.

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Here it's called nitrogen elsewhere it's simply n? Can we use nitrogen all-over?

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I would like to stick to ElemRV-N at board level since that's the actual chip name. I'm fine with renaming the device-tree to elemrn-nitrogen.dtsi if that makes it better.

# Copyright (c) 2025 aesc silicon
# SPDX-License-Identifier: Apache-2.0

config SOC_FAMILY_AESC_VEXRISCV
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I'm a bit confused by the whole aesc, vexrisc, nitrogen, elemrv, n naming here. Is the family really vexriscv?

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Actually after checking this comment I figured out that SOC_FAMILY_AESC_VEXRISCV is wrong and not required at all. I removed all these configs here.

dnltz added 2 commits May 9, 2025 19:01
aesc silicon is a startup focused on developing open-source
silicon solutions.

Link: https://github.com/aesc-silicon/ElemRV

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
aesc silicon is a startup focused on developing open-source
silicon solutions.

Add a new platform to the MAINTAINERS file to ensure changes
get reviewed.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
@dnltz dnltz force-pushed the WIP/dnltz/elemrv-n-board branch from a62e2ac to e34bf89 Compare May 9, 2025 17:13
@dnltz dnltz requested a review from henrikbrixandersen May 10, 2025 10:58
@@ -0,0 +1,100 @@
/** @file
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This seems too vendor-specific to be placed here, should this be in soc/aesc/... and exposed via zephyr_include_directories(.) instead?

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@dnltz dnltz May 12, 2025

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good idea! I was not very happy about the location too.

@dnltz dnltz force-pushed the WIP/dnltz/elemrv-n-board branch from e34bf89 to 02b631a Compare May 12, 2025 09:24
@dnltz dnltz requested a review from ycsin May 12, 2025 09:29
dnltz added 5 commits May 12, 2025 17:08
Currently, the only available platform is Nitrogen, featuring a
VexRiscv CPU that boots from external SPI flash and runs code from
external HyperRAM.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add minimal support for the aesc silicon UART IP core.

This core includes an internal clock divider and supports flexible
frame configurations, allowing for variable data length, parity, and
stop bit settings.

The current driver version does not support interrupts.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
ElemRV-N is based on the nitrogen SoC platform. Add the
base nitrogen device-tree and one for elemrv-n. The elemrv-n
device-tree will contain all IP cores later.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
ElemRV-N is an end-to-end open-source microcontroller. This patch
adds basic support for the platform with any interfaces. They will
be added later since drivers are missing completly.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add a note about initial support for ElemRV-N.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
@dnltz dnltz force-pushed the WIP/dnltz/elemrv-n-board branch from 02b631a to f780572 Compare May 12, 2025 15:09
@dnltz dnltz requested a review from fkokosinski May 12, 2025 15:10
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@kartben kartben merged commit 55e8966 into zephyrproject-rtos:main May 14, 2025
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area: Devicetree area: Process area: RISCV RISCV Architecture (32-bit & 64-bit) area: UART Universal Asynchronous Receiver-Transmitter Release Notes To be mentioned in the release notes
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9 participants