drivers/espi: ite: Refactor eSPI driver support for SoC flexibility #90640
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Move register definitions from chip_chipregs.h into espi_it8xxx2.c to make the driver more adaptable to different SoCs. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
…_ESPI If CONFIG_ESPI is defined, use 0xA4 (eSPI mode). Otherwise, use 0xA5 (LPC mode). Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Renamed two functions and a macro to use more generic names, removing chip-specific identifiers. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
We have to disable eSPI pad before changing PLL sequence or sequence will fail if CS# pin is low. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
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brockus-zephyr,
Dino-Li,
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keith-zephyr,
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| #define ESPI_IT8XXX2_SOC_DEV DEVICE_DT_GET(DT_NODELABEL(espi0)) | ||
| #define ESPI_ITE_SOC_DEV ESPI_IT8XXX2_SOC_DEV |
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Nit - do you need both macros?
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I kept ESPI_IT8XXX2_SOC_DEV because it's still used in some parts of espi_it8xxx2.c. So for now, both macros are needed.
keith-zephyr
approved these changes
Jun 4, 2025
Dino-Li
approved these changes
Jun 5, 2025
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Hi @nordic-krch, could you please take a look at this PR? Thanks! |
nordic-krch
approved these changes
Jun 5, 2025
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This PR includes the following improvements:
Register definitions previously located in a shared header file have been moved into the driver source file. This reduces cross-dependencies and makes the driver easier to adapt for different SoCs. Chip-specific function and macro names were also renamed to more generic forms to align with the SoC-common structure.
Added necessary configurations when CONFIG_ESPI is enabled, including disabling the eSPI pad before changing the PLL sequence and setting the appropriate mode in vector.S.